69
HCD-GTX66/GTX77
IC401 M30622MGP-A57FPU0 (SYSTEM CONTROL) (MAIN BOARD (1/4))
Pin No.
Pin Name
I/O
Pin Description
1
XRST
O
Reset signal output to the digital signal processor “L”:reset
2
MMUTE
O
Control port for the digital signal processor motor driver mute
3
CD CCE
O
Chip enable contor port to the digital signal processor
4
SIRCS
I
Remote control signal input
5
CD CLK
O
Serial date transfer clock signal output to the digital signal processor
6
MP3 IREQ
I
Digital signal decoder request pin to master control
7
SOURCE SEL1
O
Select function input for effector mode (CD/USB/Video in: “L”,
Tuner/Tape/Audio in: “H”)
8
BYTE
—
Ground pin
9
CNVss
—
Ground pin
10
XC IN
I
Sub system clock input (32.768 kHz)
11
XC OUT
O
Sub system clock output (32.768 kHz)
12
RESET
I
System reset signal input from the reset signal IC “L”: reset After the power
supply rises, “L” is input for several hundreds msec and then change to “H”.
13
X OUT
O
Main system clock output (5 MHz)
14
VSS
—
Ground pin
15
X IN
I
Main system clock input (5 MHz)
16
VCC
—
Power supply pin (+3.3 V)
17
NMI
I
Non-maskable interrupt input
18
SOURCE SEL2
O
Select function input for effector mode (CD/USB/Tuner/Tape: “H”,
Audio in/Video in: “L”)
19
SBSY
I
Subcode sync detection signal input from the digital signal processor
20
AC CUT
I
AC off detection signal input from the reset signal IC “L”: AC Cut detected
21
BUS3
I/O
Data bus line for CD communication with master control
22
BUS2
I/O
Data bus line for CD communication with master control
23
BUS1
I/O
Data bus line for CD communication with master control
24
BUS0
I/O
Data bus line for CD communication with master control
25
EFFECTOR S0
O
Effector circuitry delay time selection bit 0 signal output
26
EFFECTOR S1
O
Effector circuitry delay time selection bit 1 signal output
27
EFFECTOR S2
O
Effector circuitry delay time selection bit 3 signal output
28
EFFECTOR SEL
O
Effector circuity bypass control signal output “H”: bypass
29
IIC CLK
I/O
Clock signal for IIC communication between Master controller and Display controller
30
IIC DATA
I/O
Data signal for IIC communication between Master controller and Display controller
O
Reset signal output to USB control IC “L”: reset
O
Power on/off control signal output to BU section “H”: power on
O
LED drive signal output of power indicator and fan on/off control port
I
Serial send control signal input from USB IC
O
UART serial transmission data line signal output to USB IC
I
UART serial reception data line signal output from USB IC
O
Reset signal output to display control IC “L”: reset
USB SERIAL RTS0
O
Serial receive control output from USB IC
O
USB and CD control switch CD (H)/USB (L)
40
USB PWR
O
Power on/off control signal output to USB section Power On: H
41
OPEN SW
I
Eject detection signal input from the CD mechanism
42
TBL SENSE
I
Disc tray position detection signal input from the CD mechanism
43
E-3
I
Disc tray status detection signal input from the CD mechanism
44
E-2
I
Disc tray status detection signal input from the CD mechanism
45
E-1
I
Disc tray status detection signal input from the CD mechanism
46
TMF
O
CD mechanism turning motor control signal output
47
TMR
O
CD mechanism turning motor control signal output
48
LMF
O
CD mechanism loading motor control signal output
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