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32
ANALOG
DIGIT
AL
RCLK
NC
XO
XI
VSS2
T2
VDD2
T1
QUAL
RDA
T
VREF
MUX
VDD1
VSS1
VSS3
CMP
1
4
3
6
5
8
7
2
14
15
16
13
12 11 10
9
CLOCK
PLL 57kHz
RDS/ARI
COMPARATOR
8th SWITCHED
CAPACITOR
FILTER
ANTI-ALIASING
FILTER
BIPHASE
DECODER
PLL
1187.5Hz
DEFFERENTIAL
DECODER
TEST
– PANEL Board –
6
7
8
9
10
16
15
14
13
12
11
CK
E
F
G
H
QH
D
C
B
A
SERIAL
IN
CLOCK
INHIBIT
SHIFT/
LOAD
GND
QH
VCC
OUTPUT
QH
SERIAL
INPUT
A
B
C
D
CLOCK
INHIBIT
H
OUTPUT
QH
PARALLEL INPUTS
1 2
3
4
5 6 7 8 9
10
16 15 14 13 12 11
CONTROL
CIRCUIT
12 BIT
SHIFT
REGISTER
12 BIT
STORAGE
REGISTER
OUTPUT
BUFFER
(OPEN DRAIN)
17
18
VDD
OE
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
LCK
CLOCK
DATA
VSS
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