43
DVX-100
•
MPEG BOARD IC801 MB91101APFV-G-BND (CPU)
Pin No.
Pin Name
I/O
Description
1
CSIL
O
Not used (open)
2
CSIH
O
Not used (open)
3
/DWI
O
Not used (open)
4
VCC3
—
Power supply terminal (+3.3V)
5
CLK
O
System clock signal output
6, 7
/CS5, /CS4
O
Not used (open)
8 to 11
/CS3 to /CS0
O
Chip select signal output
12
/NMI
I
Non-maskable interrupt input terminal Fixed at “H” in this set
13
/HST
I
Not used (fixed at “H”)
14
/RST
I
Reset signal input
15
VSS
—
Ground terminal
16 to 18
MD0 to MD1
I
Mode setting terminal Fixed at “L” in this set
19
/RDY
I
Ready signal input
20
/BGRNT
O
Not used (open)
21
BRD
O
Not used (open)
22
/RD
O
Read enable signal output
23, 24
/WR0, /WR1
O
Write enable signal output
25 to 39
D16 to D30
I/O
Two-way data bas
40
VSS
—
Ground terminal
41
D31
I/O
Two-way data bas
42
A0
O
Address signal output
43
VCC5
—
Power supply terminal (+3.3V)
44 to 64
A1 to A21
O
Address signal output
65
VSS
—
Ground terminal
66 to 68
A22 to A24
O
Address signal output Not used (pull up)
69
AVCC
—
Power supply terminal (+3.3V)
70
AVRH
I
Reference voltage input (+3.3V) terminal
71
AVSS
—
Ground terminal
72 to 75
AN0 to AN3
I
Setting terminal for the version Fixed at “L”
76
SI0
I
RS-232C serial data input
O
RS-232C serial data output
O
DVD/CD switching signal output
O
Muting control signal output
O
Not used (open)
O
Not used (open)
I
NTSC/PAL setting terminal “L”: PAL, “H”: NTSC
O
Not used (open)
O
Not used (open)
90
VSS
—
Ground terminal
91
X1
O
System clock output terminal (12.5MHz)
92
X0
I
System clock input terminal (12.5MHz)
93
VCC5
—
Power supply terminal (+3.3V)
94
INT1
O
Not used (open)
95
NINT0
I
Interrupt status input
96
RAS0
O
Row address strobe signal output
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