Sony DVP-S325, Руководство по обслуживанию

Страница: 90 / 134

5-1 E
SECTION 5
IC PIN FUNCTION DESCRIPTION
D
VP-S325/S525D/S725D
Pin No. Pin name I/O Function
68 EOP0 I Not used
69 AVCC - Power supply
70 AVRH - Reference power supply (+3.3V)
71 AGND - Ground
72 AN0 I Set of mode 0
73 AN1 I Set of mode 1
74 AN2 I Set of mode 2
75 AN3 I Set of mode 3 (fixed at “H”)
76 SI0 I Serial data input from IF CON and EEPROM
77 SO0 O Serial data output to IF CON and EEPROM
78 SC0 O Serial clock output to IF CON and EEPROM
79 SI1 I Serial bus 1 (for data input)
80 SO1 O Serial bus 1 (for data output)
81 SI2 I Serial bus 2 (for data input)
82 SO2 O Serial bus 2 (for data output)
83 PF7 O Reset signal output
84 DACK1 O Output of DMA-ACK 0 to AV DEC
85 DACK0 O Output of DMA-ACK 1 to AV DEC
86 DREQ1 I Input of DMA-REQ 0 from AV DEC
87 DREQ0 I Input of DMA-REQ 1 from AV DEC
88 INT3 I Input of interrupt from HGA
89 SC1 O Serial clock output
90 GND - Ground
91 X1 O Clock output (12.5MHz)
92 X0 I Clock input (12.5MHz)
93 VCC5 - Power supply
94 INT1 I Input of interrupt ARP and SERVO DSP
95 INT0 I Input of interrupt from AV DEC
96 PB0 I Rear panel lime input select (“H”: DISC “L”: EXT)
97 PB1 O Chip select signal to IF CON
98 PB2 O Chip select signal to DAC (Lt and Rt)
99 PB3 O Chip select signal to DAC (L and R)
100 PB4 O DVD/CD select (“H”: 44.1kHz “L”: 48kHz)
5-1. SYSTEM CONTROL PIN FUNCTION (MB-82/85 BOARD IC202)
Pin No. Pin name I/O Function
1 PB5 O Analog filter gain control
2 PB6 O VES gain control “H”: VES
3 PB7 O Rear CH boost control “H”: rear boost
4 VCC3 - Power supply
5 CLK O CPU clock out (25 MHz)
6 CS5 O Not used
7 CS4 O Chip select signal for ARP, SERVO DSP and HGA
8 CS3 O Chip select signal for SDRAM and AV DEC
9 CS2 O Chip select signal for REG and AV DEC
10 CS1 O Chip select signal for external SRAM
11 CS0 O Chip select signal for external FLASH ROM
12 NMI I Not used (fixed at “H”)
13 HST I Not used (fixed at “H”)
14 RST I Reset signal input from IF CON
15 GND - Ground
16 MD0 I Input of mode select 0 (fixed at “1”)
17 MD1 I Input of mode select 1 (fixed at “0”)
18 MD2 I Input of mode select 2 (fixed at “0”)
19 RDY I Wait signal input
20 P81 I Test terminal (fixed at “H”)
21 P82 I Test terminal (fixed at “L”)
22 RD O Read enable signal output
23 WR0 O High byte write enable signal output (16 bit and 8 bit)
24 WR1 O Low byte write enable signal output (16 bit only)
25-32 D16-D23 I/O Data bus D0-D7 (16 bit)
33-39 D24-D30 I/O Data bus D8-D14 (16 bit), D0-D6 (8 bit)
40 GND - Ground
41 D31 I/O Data bus D15 (16 bit), D7 (8 bit)
42 A00 O Address bus A0
43 VCC5 - Power supply
44-64 A01-A21 O Address bus A1-A21
65 GND - Ground
66 P66 O PLL IC control output “H”: DOUBLE
67 P67 I DIAG mode signal input “L”: DIAG