58
DVP-NW50
Pin No.
Pin Name
I/O
Description
98
AXR0[10]
I/O
McASP0 TX/RX data (not used)
99
AXR0[9]
I/O
McASP0 TX/RX data (not used)
100
AXR0[8]
I/O
McASP0 TX/RX data (not used)
101
CVDD
—
Power supply +1.25V
102
ACLKX1
O
SCLK signal output
103
DVDD
—
Power supply +3.3V
104
CVDD
—
Power supply +1.25V
105
AMUTE1
I
Mute control signal input
106
VSS
—
Ground terminal
107
AFSX1
O
LRCLK signal output
108
GP0[0]
—
Not used
109
VSS
—
Ground terminal
110
AHCLKX1
I
MCLK signal input
111
GP0[8]
—
Not used
112
AHCLKR1
O
MCASP1 receive high-frequency master clock (not used)
113
GP0[3]
—
Not used
114
CVDD
—
Power supply +1.25V
115
VSS
—
Ground terminal
116
GP0[9]
—
Not used
117
GP0[10]
—
Not used
118
GP0[11]
—
Not used
119
GP0[12]
—
Not used
120
CVDD
—
Power supply +1.25V
121
GP0[13]
—
Not used
122
GP0[14]
—
Not used
123
GP0[15]
—
Not used
124
DVDD
—
Power supply +3.3V
125
RESET
I
Reset signal input
126
VSS
—
Ground terminal
127
CVDD
—
Power supply +1.25V
128
CVDD
—
Power supply +1.25V
129
EMU1
I/O
Select the device functional mode of operation (not used)
130
EMU0
I/O
Select the device functional mode of operation (not used)
131
TDO
I/O
JTAG test-port data out (not used)
132
DVDD
—
Power supply +3.3V
133
TDI
I
JTAG test-port data in (not used)
134
TMS
I
JTAG test-port mode select (not used)
135
TCK
I
JTAG test-port clock (not used)
136
VSS
—
Ground terminal
137
CVDD
—
Power supply +1.25V
138
TRST
I
JTAG test-port reset.
139
RSV
—
Not used
140
VSS
—
Ground terminal
141
CVDD
—
Power supply +1.25V
142
PLLHV
—
Power supply +3.3V
143
RSV
—
Ground terminal
144
CLKIN
I
Clock input