5-1 E
SECTION 5
IC PIN FUNCTION DESCRIPTION
DVP-C650D/C653D
Pin No.
Pin name
I/O
Function
68
EOP0
I
Not used
69
A
VCC
-
Po
wer suppl
y
70
A
VRH
-
Reference po
wer suppl
y (+3.3V)
71
A
GND
-
Ground
72
AN0
I
Set of mode 0
73
AN1
I
Set of mode 1
74
AN2
I
Set of mode 2
75
AN3
I
Set of mode 3 (f
ixed a
t
“H”)
76
SI0
I
Serial da
ta input from IF CON and EEPR
OM
77
SO0
O
Serial da
ta output to IF CON and EEPR
OM
78
SC0
O
Serial c
lock output to IF CON and EEPR
OM
79
SI1
I
Serial b
us 1 (for da
ta input)
80
SO1
O
Serial b
us 1 (for da
ta output)
81
SI2
I
Serial b
us 2 (for da
ta input)
82
SO2
O
Serial b
us 2 (for da
ta output)
83
PF7
O
Reset signal output
84
DA
CK1
O
Output of DMA-A
CK 0 to
A
V DEC
85
DA
CK0
O
Output of DMA-A
CK 1 to
A
V DEC
86
DREQ1
I
Input of DMA-REQ 0 from
A
V DEC
87
DREQ0
I
Input of DMA-REQ 1 from
A
V DEC
88
INT3
I
Input of interrupt from HGA
89
SC1
O
Serial clock output
90
GND
-
Ground
91
X1
O
Clock output (12.5MHz)
92
X0
I
Clock input (12.5MHz)
93
VCC5
-
Po
wer suppl
y
94
INT1
I
Input of interrupt
ARP and SER
V
O DSP
95
INT0
I
Input of interrupt fr
om
A
V DEC
96
PB0
I
Rear panel lime input select (“H”: DISC “L”: EXT)
97
PB1
O
Chip select signal to IF CON
98
PB2
O
Chip select signal to D
A
C (Lt and Rt)
99
PB3
O
Chip select signal to D
A
C (L and R)
100
PB4
O
D
VD/CD select (“H”: 44.1kHz
“L”: 48kHz)
5-1.
SYSTEM CONTR
OL PIN FUNCTION (MB-85 BO
ARD IC202)
Pin No.
Pin name
1
PB5
2
PB6
3
PB7
Rear CH boost control “H”: rear boost
4
VCC3
5
CLK
6
CS5
O
Not used
7
CS4
O
Chip select signal f
or
ARP
, SER
V
O DSP and HGA
8
CS3
O
Chip select signal f
or SDRAM and
A
V DEC
9
CS2
O
Chip select signal f
or REG and
A
V DEC
10
CS1
O
Chip select signal f
or e
xternal SRAM
11
CS0
O
Chip select signal f
or e
xternal FLASH R
OM
12
NMI
I
Not used (fix
ed a
t
“H”)
13
HST
I
Not used (fix
ed a
t
“H”)
14
RST
I
Reset signal input from IF CON
15
GND
-
Ground
16
MD0
I
Input of mode select 0 (f
ixed a
t
“1”)
17
MD1
I
Input of mode select 1 (f
ixed a
t
“0”)
18
MD2
I
Input of mode select 2 (f
ixed a
t
“0”)
19
RD
Y
I
W
ait signal input
20
P81
I
T
est ter
minal (f
ixed a
t
“H”)
21
P82
I
T
est ter
minal (f
ixed a
t
“L”)
22
RD
O
Read enable signal output
23
WR0
O
High byte write enable signal output (16 bit and 8 bit)
24
WR1
O
Low b
yte wr
ite ena
ble signal output (16 bit onl
y)
25-32
D16-D23
I/O
Data b
us D0-D7 (16 bit)
33-39
D24-D30
I/O
Data b
us D8-D14 (16 bit), D0-D6 (8 bit)
40
GND
-
Ground
41
D31
I/O
Data b
us D15 (16 bit), D7 (8 bit)
42
A00
O
Address b
us
A0
43
VCC5
-
Power suppl
y
44-64
A01-A21
O
Address b
us
A1-A21
65
GND
-
Ground
66
P66
O
PLL IC control output “H”: DOUBLE
67
P67
I
DIA
G mode signal input “L”: DIA
G
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