4-6
SIU-100/100T
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AGND
VSENSE
IN
COMP
OUT
PWRGD
OUT
BOOT
IN
PH
I/O
PH
I/O
PH
I/O
PH
I/O
PH
I/O
RT
IN
SYNC
IN
SS/ENA
I/O
VBIAS
OUT
V
IN
V
IN
V
IN
PGND
PGND
PGND
INPUTS
BOOT
RT
SYNC
VSENSE
OUTPUTS
COMP
PWRGD
VBIAS
INPUTS/OUTPUTS
PH
SS/ENA
OTHERS
AGND
PGND
V
IN
: BOOTSTRAP
: FREQUENCY SETTING RESISTOR
: SYNCHRONIZATION
: ERROR AMPLIFIER INVERTING
: ERROR AMPLIFIER
: POWER GOOD (OPEN DRAIN)
: INTERNAL BIAS REGULATOR
: PHASE
: SLOW-START/ENABLE
: ANALOG GROUND
: POWER GROUND
: POWER SUPPLY
SYNCHRONOUS BUCK PWM SWITCHER
—TOP VIEW—
TPS54310PWPR (TI)
S
OFFSET
ENABLE
COMP.
0.8 V
V
IN
V
IN
V
IN
UVLO
1 - 4
u
s
FALLING EDGE
DELAY
RISING EDGE
DELAY
RISING EDGE
DELAY
SAMPLING
LOGIC
ILIM
COMP.
VI (LIM)
HIGH
DR
HIGH
DR
HIGH
IN
VBIAS
UVLO
VPHASE
SHUTDOWN
HIGH
IN
UVLO
DEAD TIME
OSC.
MUX
DELAY
T SUNT
REF/DAC
R
S
Q
REG.
S
S
S
S
20 - 50
u
s
FALLING EDGE
DELAY
POWER GOOD
COMP.
PWM
COMP.
V
IN
UVLO
COMP.
ERROR
AMP.
+
_
BIAS UVLO
SS
DIS
BG GOOD
+
C
T
VSENSE
I
SET
V
PGD
SS/ENA
18
VSENSE
2
COMP
SYNC
RT
AGND
3
19
20
1
VBIAS
17
V
IN
14 - 16
BOOT
5
PH
6 - 10
PGND
11 - 13
PERGD
4
IC
STEREO AUDIO VOLUME CONTROL
—TOP VIEW—
: CHIP SELECT
: MUTE CONTROL
: SERIAL DATA
: SERIAL CLOCK
: L/R CH ANALOG
: ZERO-CROSS ENABLE
: SERIAL DATA
: L/R CH ANALOG
INPUTS
CS
MUTE
SDI
SCLK
V
IN
L, V
IN
R
ZCEN
OUTPUTS
SDO
V
OUT
L, V
OUT
R
1
2
3
4
5
6
7
8
ZCEN
IN
CS
IN
SDI
IN
DV
CC
DGND
SCLK
IN
SDO
OUT
MUTE
IN
16
15
14
13
12
11
10
9
V
IN
L
IN
AGNDL
V
OUT
L
OUT
AV
CC
AV
CC
V
OUT
R
OUT
AGNDR
V
IN
R
IN
AGNDL
15
+
_
MUX
MUX
SERIAL
CONTROL
PORT
V
IN
L
16
V
OUT
L
14
AGNDR
10
V
IN
R
9
MUTE
8
SCLK
6
SDI
3
SDO
7
V
OUT
R
11
CS
2
ZCEN
1
8
8
8
8
+
_
PGA2310UA/1K (BURR-BROWN)
Содержание DMBK-S101
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Страница 162: ...Printed in Japan Sony Corporation 2003 7 08 2003 SIU 100 SY SIU 100T SY E 9 976 912 01 ...