6-8
DSC-WX70_L3
Note: IC211 is not supplied, but this is included
in SY-331 COMPLETE BOARD (SERVICE).
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
A
B
C
D
E
F
08
SY-331 BOARD (6/8)
CPU, CAMERA DSP, AV SIGNAL PROCESS,
LENS CONTROL, MODE CONTROL, HDMI
PROCESS (3/3)
XX MARK: NO MOUNT
C373
2.2u
REG_GND
C358
2.2u
REG_GND
C370
0.1u
C368
2.2u
R351
240
REG_GND
C371
0.1u
K10 VSS
K11 VSS
K12 VSS
K13 VSS
K19 VSS
K20 VSS
K22 VSS
K23 VSS
L10
VSS
L11
VSS
L12
VSS
L13
VSS
L18
VSS
L19
VSS
M10 VSS
M11 VSS
M12 VSS
M13 VSS
M14 VSS
M15 VSS
M16 VSS
M17 VSS
M18 VSS
M19 VSS
N10 VSS
N11 VSS
N12 VSS
N13 VSS
N14 VSS
N15 VSS
N16 VSS
N17 VSS
N18 VSS
N19 VSS
P10 VSS
P11 VSS
P12 VSS
P13 VSS
P14 VSS
P15 VSS
P16 VSS
P17 VSS
P18 VSS
P19 VSS
Y13 VSS
Y14 VSS
Y15 VSS
Y16 VSS
Y17 VSS
A1
N.C.
A2
N.C.
B1
N.C.
AH1 N.C.
AJ1 N.C.
AJ2 N.C.
R10
VSS
R11
VSS
R12
VSS
R13
VSS
R14
VSS
R15
VSS
R16
VSS
R17
VSS
R18
VSS
R19
VSS
T10
VSS
T11
VSS
T12
VSS
T13
VSS
T14
VSS
T15
VSS
T16
VSS
T17
VSS
T18
VSS
T19
VSS
T25
VSS
U10
VSS
U11
VSS
U12
VSS
U13
VSS
U14
VSS
U15
VSS
U16
VSS
U17
VSS
U18
VSS
U19
VSS
U20
VSS
U25
VSS
V10
VSS
V11
VSS
V12
VSS
V13
VSS
V14
VSS
V15
VSS
V16
VSS
V17
VSS
V18
VSS
W13
VSS
W14
VSS
W15
VSS
W16
VSS
W17
VSS
AB1
VSS
AJ28
N.C.
AJ29
N.C.
AH29
N.C.
A28
N.C.
A29
N.C.
B29
N.C.
W1 VDD_CORE
W2 VDD_CORE
W4 VDD_CORE
W5 VDD_CORE
W7 VDD_CORE
W8 VDD_CORE
W10 VDD_CORE
W11 VDD_CORE
W12 VDD_CORE
Y1 VDD_CORE
Y2 VDD_CORE
Y4 VDD_CORE
Y5 VDD_CORE
Y7 VDD_CORE
Y8 VDD_CORE
Y10 VDD_CORE
Y11 VDD_CORE
V1 IOVDD11_DDR
V2 IOVDD11_DDR
V4 IOVDD11_DDR
V5 IOVDD11_DDR
V7 IOVDD11_DDR
V8 IOVDD11_DDR
C1 VDD12_POP_DDR
P1 VDD12_POP_DDR
AC1 VDD12_POP_DDR
AJ9 VDD12_POP_DDR
F29 VDD12_POP_DDR
A25 VDD12_POP_DDR
A7 VDD12_POP_DDR
C2 VDD12_POP_DDR
AH9 VDD12_POP_DDR
B25 VDD12_POP_DDR
B7 VDD12_POP_DDR
A8 VSS
A24 VSS
E1 VSS
E5 VSS
F5
VSS
G7 VSS
G8 VSS
G9 VSS
G10 VSS
H9 VSS
H10 VSS
H21 VSS
N7 VSS
N8 VSS
P4 VSS
P5 VSS
P7 VSS
P8 VSS
P25 VSS
T4
VSS
T5
VSS
T7
VSS
T8
VSS
V22 VSS
V23 VSS
AJ8 VSS
AJ21 VSS
G28 DDR_ZQ
U1
IOVDDCA_DDR
U2
IOVDDCA_DDR
U4
IOVDDCA_DDR
U5
IOVDDCA_DDR
U7
IOVDDCA_DDR
U8
IOVDDCA_DDR
R1
IOVDDQ_DDR1
R2
IOVDDQ_DDR1
R4
IOVDDQ_DDR1
R5
IOVDDQ_DDR1
R7
IOVDDQ_DDR1
R8
IOVDDQ_DDR1
AA1
IOVDDQ_DDR2
AA2
IOVDDQ_DDR2
AA4
IOVDDQ_DDR2
AA5
IOVDDQ_DDR2
AA7
IOVDDQ_DDR2
AA8
IOVDDQ_DDR2
T1
DDRVREF_DQ
T2
VSS
G29
DDRVREF_CA
J23
VSS
P2
VDD18_POP_DDR
AC2
VDD18_POP_DDR
F28
VDD18_POP_DDR
AH20
VDD18_POP_NAND
AJ20
VDD18_POP_NAND
AD28
VDD18_POP_NAND
AD29
VDD18_POP_NAND
AB2
VSS
AB7
VSS
AB8
VSS
AB13
VSS
AB14
VSS
AB15
VSS
AB16
VSS
AB17
VSS
AC8
VSS
AC13
VSS
AC14
VSS
AC17
VSS
AC18
VSS
AD1
VSS
AD2
VSS
AE7
VSS
AE10
VSS
AE11
VSS
AE12
VSS
AE17
VSS
AE28
VSS
AE29
VSS
AF7
VSS
AF11
VSS
AG1
VSS
AG2
VSS
AH8
VSS
Y12
VPGM
REG_GND
REG_GND
C356
XX
REG_GND
C363
XX
REG_GND
D_VID
REG_GND
REG_GND
C369
0.1u
DDR_1.8V
DD_1.8V
C360
0.1u
C357
0.1u
C354
XX
C352
2.2u
C351
XX
C364
XX
DDR_1.2V
DDR_1.2V
DD_1.2V
C361
0.1u
C359
0.1u
C372
0.001u
C367
0.001u
C365
0.001u
FB351
C362
XX
C353
XX
C366
0.1u
C374
XX
R353
XX
CORE VDD
LENS CONTROL, MODE CONTROL, HDMI PROCESS
OLY1G2G06A
IC211 (5/6)
CPU, CAMERA DSP, AV SIGNAL PROCESS,
OLY1G2G06A
IC211 (6/6)
CPU, CAMERA DSP, AV SIGNAL PROCESS,
LENS CONTROL, MODE CONTROL, HDMI PROCESS
