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CX-J3000/J3000M
17
17
CX-J3000/J3000M
SECTION 7
DIAGRAMS
7-1.
BLOCK DIAGRAM – SERVO SECTION –
A
C
B
F
E
D
A
C
B
D
LD
PD
VR
F
T+
T–
F+
F–
SL+
SL–
SP+
SP–
E
VREF
LD
PD
LD POWER
CONTROLLER
Q701
APC
FIN2
FIN1
LDD
LDS
TIN2
TIN1
VREF
RF
10
9
11
80
7
79
4
8
20
17
18
TRACKING
COIL
DRIVE
10
7
FOCUS
COIL
DRIVE
TIN
FIN
25
SLIN
SLED
MOTOR
DRIVE
3
SPINDLE
MOTOR
DRIVE
SPIN
VREF
OPIN
MUTE
T+
T–
12
11
F+
F–
26
27
SL+
SL–
2
1
SP+
SP–
(TRACKING)
(FOCUS)
OPTICAL PICK-UP
BLOCK
(KSM-213RDP)
M
M
M702
(SLED)
M701
(SPINDLE)
SLED/SPINDLE
MOTOR DRIVER,
TRACKING/FOCUS
COIL DRIVER
IC702
(CX-J3000)
(CX-J3000M)
S701
(LIMIT)
EFMIN
HFL
AGC
PH(RFENV)
FE
TE
VREF
CONT1
FSEQ
CONT4
DRF
RES
DI
CE
CL
WRQ
DO
XOUT
XIN
LCHO
RCHO
DATA
DATACK
LRSY
ASDFIN
ASDACK
ASLRCK
CF2
FSX/16MIN
16MOUT
3
67
TDD
TD
FD
SP
SL
31
72 25
66
63 61 62
49
48
73
74
75
76
77
78
80
1
2
3
4
5
9
59
58
57
56
55
52
50
65 64
42
45
RF AMP,
SYSTEM SERVO PROCESSOR,
DIGITAL SIGNAL PROCESSOR
IC701
(CX-J3000)
(CX-J3000M)
22
9 28
3 100 5 25 4
1
X701
16.93MHz
O_CD_CE
O_CD_DATA
O_CD_CLK
I_CD_WRQ
O_CD_RST
I_CD_DRF
I_MP3_FSEQ
I_CD_DATA
27
99
O_MP3_CE/O_AMP_ON
I_MP3_INTB/I-HP
HP-ON
AMP-ON
I_CD_LID
SYSTEM CONTROLLER
IC801 (1/3)
CLV,CAV
CONTROL
PLL
VCEC
SWITCH
ERROR
CORRECTION
AUDIO CD
A/D
CONVERTER,
SERVO
PROCESSOR
FRAME SYNC
DETECT,PROTECT
INSERT
EFM DECODER
INTERPOLATION
MUTE
&
ATTENUATION
DEEMPHASIS
8FS
DIGITAL
FILTER
&
1-bit DAC
SERIAL
OUT
EXTERNAL
AUDIO IN
LPF
SLICE
LEVEL
CONTROL
GENERAL
PURPOSE
PORT
COMMAND
INTERFACE
CLOCK
GENERATOR
23
15
FD
SL
SP
TD
VREF
VREF
VREF
R-CH
DATACK
LRSY
79
60
DATA IN
ADDATA
ADBCK
ADLRCK
CF2IN
WEB
OEB
CASLB
CASUB
RASB
CKOUT
7
54
41 44 43 45 42
16 30 31 29 15
23-30,33-40
60-53,50
18-21,24-28
2-5,7-10,
35-38,40-43
CKIN
CMDOUT
CMDIN
CL
CE
INTB
RESB
CD-L
D/A
CONVERTER
PH/BH
20
FDD
SPDO
SLDO
21 22 23
MDATA0
I
MDATA15
MADRS0
I
MADRS8
WE
OE
LCAS
UCAS
RAS
DQ0-DQ15
A0-A8
MP3 DECODER,
CD-ROM DECODER,
ANTI-SHOCK
CONTROLLER
IC1001
SDRAM
IC1002
S851
CD LID OPEN/CLOSE
DETECT
• SIGNAL PATH
: CD PLAY
•
R-ch is omitted due to same as L-ch.
(J3000M)
(J3000)
B
A
(Page 19)
(Page 19)
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