Sony CDX-V3800, Руководство по обслуживанию

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29
CDX-V3800
• IC400 SPCA717A-HL211 (VIDEO SIGNAL PROCESSOR) (SERVO BOARD (2/2))
Pin No. Pin Name I/O Pin Description
1 FSADJUST —
Full-Scale adjust control pin The Full-Scale current of D/A converters can be
adjusted by connecting a resistor (RESET) between this pin and ground.
2 COMP —
Compensation pin A0.1 µ F ceramic capacitor must be used to bypass this pin to VAA.
The lead length must be kept as short as possible to avoid noise.
3 AVCC — Analog power supply pin (+3.3 V)
4 VREF OUT O
Voltage reference signal output It generates typical 1.2 V voltage reference and may
be used to drive pin
5
(VREF IN) directly.
Voltage reference signal input An external voltage reference must supply typical
5 VREF IN I
1.235 V to this pin. A0.1 µ F ceramic capacitor must be used to de-couple this input
to ground. The decoupling capacitor must be as closed as possible to minimize the
length of the load. The pin may be connected derectry to pin 4 (VREF OUT).
6 VBIAS — DAC bias voltage Potential normally 0.7 V less than pin 2 (COMP).
7 NC — Not used. (Open)
8 AGND — Analog ground pin
Power save mode A logic high on this pin puts the chip into power-down mode. This
9 SLEEP I pin is equal to reset pin. An external logic high pulse should input to the pin when
power on.
10 SVIDEO I
Video signal selection pin A logic high selects Y output. A logic low selects
composite video output. Not used in this set. (Fixed at “L”.)
11 CBSWAP I
Cr and Cb pixel sequence configuration pin A logic high swap the Cr and Cb sequence.
Not used in this set. (Fixed at “L”.)
12 MASTER I
Master/Slave mode selection A logical high for master mode operation. A logical 0
for slave mode operation. Not used in this set. (+3.3 V)
13 MODEA I Mode configuration pin Not used in this set. (Fixed at “L”.)
14 MODEB I Mode configuration pin
15 CLK I
27 MHz crystal oscillator input A crystal with 27 MHz clock frequency can be
connected between this pin and pin
qh
(XTALO).
16 XTALO O Crystal oscillator output Not used in this set. (Open)
17 to 24 P0 to P7 I
YCrCb pixel inputs
They are latched on the rising edge of CLK.
25 CLKOUT O Pixel clock signal output Not used in this set. (Open)
26 DGND — Digital ground pin
27 VDD — Digital power supply pin (+3.3 V)
28 VSYNC I/O
Vertical sync input/output
VSYNC is latched/output following the rising edge of CLK.
29 HSYNC I/O
Horizontal sync input/output
HSYNC is latched/output following the rising edge of CLK.
30 TEST I Test pin These pins must be connected to digital ground.
31 AGND — Analog ground pin.
32 CVBSY O
Composite/Luminance output. This is a high-impedance current source output. The
output format can be selected by the PAL pin. The CVBSY can drive a 37.5 Ω load.