Sony CDX-646 Operating Instructions (English,Español, Français), Руководство по обслуживанию

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6-12. IC PIN FUNCTION DESCRIPTION
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MAIN BOARD IC201 CXP740056-007R (SYSTEM CONTROLLER)
Pin No. Pin Name I/O Description
1 ESPSEL I ESP on/off setting terminal Not used (fixed at “L”)
2 ML O
Normal/high speed playback control signal output terminal “L”: high speed playback
Not used (open)
3 EMPHO O Emphasis signal output terminal Not used (open)
4 AMUTE O Audio line muting on/off control signal output terminal “H”: muting on
5 CDXLT O Serial data latch pulse signal output to the CXD2598Q (IC101)
6 CDDATA O Serial data output to the CXD2598Q (IC101)
7 CDCLK O Serial data transfer clock signal output to the CXD2598Q (IC101)
8 CDON O D/A converter and servo section power supply on/off control signal output “H”: power on
9 ELVON O Mechanism deck section power supply on/off control signal output “H”: power on
10 DOUTSEL I Digital output on/off control signal input terminal “L”: digital output on Not used (open)
11 NC — Not used (open)
12 RAMWE O Data write enable signal output to the S-RAM “L”: active Not used (open)
13 to 20
RAMIO8 to
RAMIO1
I/O Two-way data bus with the S-RAM Not used (open)
21 to 28
RAMA7 to
RAMA0
O Address signal output to the S-RAM Not used (open)
29 NC — Not used (open)
30 to 36
RAMA14 to
RAMA8
O Address signal output to the S-RAM Not used (open)
37 RAMCS O Chip select signal output to the S-RAM “L”: active Not used (open)
38 RESET I
System reset signal input from the SONY bus interface (IC302) and reset signal generator (IC303)
“L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
39 GND — Ground terminal
40 XTAL O Main system clock output terminal (12 MHz)
41 EXTAL I Main system clock input terminal (12 MHz)
42 TEXTSEL I
CD text mode setting terminal “L”: CD text on, “H”: does not display track name
Not used (open)
43 SI I Serial data input from the SONY bus interface (IC302)
44 SO O Serial data output to the SONY bus interface (IC302)
45 SCLK I Serial data transfer clock signal input from the SONY bus interface (IC302)
46 CFSEL I Custom file on/off setting terminal “L” custom file on Not used (open)
47 EEINIT I Initialize signal input for the EEPROM “H”: format Not used (open)
48 EEDATA I/O Two-way data bus with the EEPROM Not used (open)
49 EECLK O Serial data transfer clock signal output to the EEPROM Not used (open)
50 VSS — Ground terminal (for A/D converter)
51 AVREF I Reference voltage (+5V) input terminal (for A/D converter)
52 VDD — Power supply terminal (+5V) (for A/D converter)
53 SINGLE I
Setting terminal for the single disc/multiple discs mode
“L”: single mode, “H”: multiple discs mode Fixed at “H” in this set (open)
54 LDON O The laser automatic power control on/off signal output “H”: automatic power control on
55 AGCHOLD O RF AGC hold on/off signal output “H”: hold
56 RFAGC I/O RF AGC level control signal output “L”: off, center voltage: 40%, “H”: 60%
57 AD I A/D input terminal Not used (open)
58 AD I A/D input terminal Not used (fixed at “L”)