Chassis
RB2G,
HE-L
143
Chassis
RB2G,
HE-L
A BOARD SCHEMATIC DIAGRAM (13 OF 24)
6
5
7
8
9
2
1
3
4
10
11
12
Rx
Tx
C
2
PART NO.
9
D
3
DESCRIPTION
10
E
4
MODEL
11
F
5
ORIGINAL
G
6
A
H
7
B
1
SHEET
8
ETH_MDC
ETH_MDC
ETH_MDIO
LED1_PHYAD1
ETH_REFCLK
RMII_CRS_DV
ETH_MDIO
RMII_RXD_1
RMII_RXD_1
RMII_RXD_0
RMII_RXD_0
RMII_TX_EN
RMII_TXD_1
RMII_TXD_0
RMII_CRS_DV
RMII_RXD_0
RMII_RXD_1
ETH_REFCLK
RMII_TX_EN
RMII_TXD_1
RMII_TXD_0
XX
R6401
GND_D
X_ETHER_PHY/WIFI_RST
005:9C;005:14I
2.49k
1/16W
R6410
1%
XX
R6409
IC6400
RTL8201FR-VB-CGT
1
RSET
2
AVDD10OUT
3
MDI+[0]/TX+
4
MDI-[0]/TX-
5
MDI+[1]/RX+
6
MDI-[1]/RX-
9
RXD[1]
10
DVDD33
11
REF_CLK
12
TXD[0]
13
TXD[1]
14
TXEN
15
PHYRSTB
16
MDC
17
MDIO
18
LED0/PHYAD[0]/PMEB/INTB
19
LED1/PHYAD[1]
20
CRS/CRS_DV
21
RXER/FXEN
22
DVDD10OUT
23
CKXTAL1
24
CKXTAL2
7
AVDD33
8
RXD[0]/CLK_CTL
XX
R6402
X_ETHER_WAKE
005:5D;009:8J
CL6400
CL6401
C6402
0.001
2kV
X7R
4520
T6400
144595511
RB6403
75
2
1
4
3
6
5
8
7
GND_D
XX
R6411
RB6402
47
RB6406
47
2
1
4
3
6
5
8
7
XX
R6414
4.7k
R6413
XX
R6417
XX
R6416
4.7k
R6415
4.7k
R6418
XX
*R6419
*D6400
XX
GND_D
XX
R6406
C6409
XX
GND_D
RB6404
47
BAX_L BOARD
ETHER
ALL resistors are in ohms,W unless otherwise noted.
ALL capacitors are in uF(p:pF)unless otherwise noted.
2013/12/05
00:16
RB2_BAX_L_PP3_041213.cir/014.sht
5004103813
RB2
14/18
To PCB System
C6400
27p
50V
CH
C6401
24p
50V
CH
JL6400
JL6401
JL6402
JL6403
4.7k
R6412
C6406
0.1
16V
X7R
1005
C6407
0.1
16V
X7R
1005
C6408
0.1
16V
X7R
1005
C6405
0.1
16V
X7R
1005
C6404
0.01
50V
X7R
1005
C6403
0.01
50V
X7R
1005
X6400 25MHz
CL6406
CL6407
CL6404
CL6403
CL6402
CL6405
STBY_+3.3V
STBY_+3.3V
STBY_+3.3V
CL6408
*IC9000
CXD4748GB
AJ24
ETHER_TX_EN
AH25
ETHER_TXD_0
AK24
ETHER_TXD_1
AJ23
ETHER_CRS_DV
AK25
ETHER_RXD_0
AJ25
ETHER_RXD_1
AH24
ETHER_MDCK
AK23
ETHER_MDIO
AH23
ETHER_REFCLK
CN6400
8P
BLK
184366411
1
2
3
4
5
6
7
8
9
10
11
12
330 R6400
FB6400
47ohm
C6410
XX
(to STBY_GPIO_15)
(from STBY_GPIO_14)
ETHER
[PHY Strap settings]
LED0/PHYAD[0]/PMEB/INTB (18pin)
0 : PHYAD[0] = LED0 = 0
-> 1 : PHYAD[0] = LED0 = 1 (default)
*An external PU is necessary in WOL mode.
LED1/PHYAD[1] (19pin)
-> 0 : PHYAD[1] = LED1 = 0 (default)
1 : PHYAD[1] = LED1 = 1
RXD[0]/CLK_CTL (8pin : internal PD)
-> 0 : REFCLK output mode (default)
1 : REFCLK input mode
RXD[1] (9pin : internal PD)
0 : 18pin supports LED function.(default)
-> 1 : 18pin supports WOL/INT function.
RXER/FXEN (21pin : internal PD)
-> 0 : UTP mode (default)
1 : Fiber mode
RMII I/F
CN6301 : RJ-45
Straight type
Please put Xtal close to IC6301.
Do not make the stub
in PWB design
as much as possible.
Rx : Differential 100
Ω
T6301 : Pulse Trans
TAIMAG
1-445-955-11
Tx : Differential 100
Ω
R6110-R6113,R6135,R6136
will be combined to networked resister.
Do not make the stub in PWB design
as much as possible.
Please put LED
on A side.
BM10: 1-814-676-11 (ECEC)
BM11: 1-814-677-11 (TopAtlantic)
For X6400:
2013/07/05 18:19
[ SOC ]
┌────────┬────────┬────────┐
│
│
60
│
60AVS
│
├────────┼────────┼────────┤
│
IC9000
│
CXD4748GB
│
CXD4748GB-1
│
└────────┴────────┴────────┘
2013/07/05 18:19
[ JIG ]
┌────────┬────────┬────────┐
│
│
No
│
Yes
│
├────────┼────────┼────────┤
│
D6400
│
XX
│
SML-310MTT86
│
├────────┼────────┼────────┤
│
R6419
│
XX
│
510
│
│
│
│
1/16W
│
│
│
│
CHIP
│
└────────┴────────┴────────┘
ETHERNET RMII
Содержание Bravia KDL-55W790B
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