Sony Bravia KDL-26T3000, Руководство по обслуживанию, Страница: 38 / 136

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R Q
P EE FF
S T U V W X Y Z AA BB CC DD
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13
0 . 1
C5040
C5024
0 . 1
0 . 1
C5028
0.1
C5020
0 . 1
C5039
0 . 1
C5043
0 . 1
C5033
0.1
C5019
0 . 1
C5029
1608
16V
0 . 1
B
C5022
0 . 1
C5032
0 . 1
C5042
0 . 1
C5023
0 . 1
C5041
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IC5002
IO/ASDO IO/nCSO
IOLVDS15p/CRC_ERROR
IO/LVDS15n/CLKUSR
VCCIO1
GND
IO/VREFB1N0
IO/LVDS8p IO/LVDS8n
TDO TMS TCK TDI
DATA0
DCLK
nCE
CLK0/VDSCLK0p/input(3) CLK1/VDSCLK0n/input(3)
GND
nCONFIG
CLK2/VDSCLK1p/input(3) CLK3/VDSCLK1n/input(3)
VCCIO1
IO/LVDS7p IO/LVDS7n
VCCINT
GND
IO/VREFB1N1
VCCIO1
IO
IO/PLL1_OUTp IO/PLL1_OUTn
GND
GND_PLL1
VCCD_PLL1
GND_PLL1
VCCA_PLL1
GNDA_PLL1
GND
IO/LVDS77n/DEV_OE
IO/LVDS77p
OI/LVDS76p
IO/LVDS76n
IO/LVDS75p
IO/LVDS75n
VCCIO4
IO/LVDS74p
IO/LVDS74n
GND
VCCINT
IO/VREFB4N1
IO/LVDS70p
IO/LVDS68p
VCCIO4
IO/LVDS68n
GND
IO/LVDS67p
IO/LVDS67n
IO/LVDS66p
IO/LVDS66n
GND
VCCINT
IO/VREFB4N0
IO/LVDS60p
IO/LVDS60n
VCCIO4
IO/LVDS59n
GND
IO/LVDS58p
IO/LVDS58n
IO/LVDS57p
IO/LVDS57n
IO/LVDS56n
IO/LVDS56p
IO/LVDS54n/INIT_DONE
IO/LVDS54p/nCEO
VCCIO3
GND
IO/VREFB3N1
GND
VCCINT
nSTATUS
CONF_DONE
MSEL1 MSEL0
IO/LVDS48n IO/LVDS48p
CLK7/LVDSCLK3n/input(3)
CLK6/LVDSCLK3p/input(3)
CLK5/LVDSCLK2n/input(3) CLK4/LVDSCLK2p/input(3)
IO/LVDS47n IO/LVDS47p IO/LVDS46n
VCCIO3
IO/LVDS46p IO/LVDS45n
GND
IO/VREFB3N0
IO/LVDS39n IO/LVDS39p
VCCIO3
IO/PLL2_OUTp IO/PLL2_OUTn
GND GND_PLL2
VCCD_PLL2
GND_PLL2
VCCA_PLL2
GNDA_PLL2
GND
IO/LVDS37n
IO/LVDS37p
IO/LVDS36n
IO/LVDS36p
VCCIO2
GND
IO/LVDS34n
IO/LVDS34p
IO/VREFB2N0
IO/LVDS33n
IO/LVDS33p
GND
VCCINT
IO/LVDS29n
IO/LVDS29p
VCCIO2
GND
IO/LVDS26p
GND
VCCINT
IO/VREFB2N1
IO/LVDS23n
IO/LVDS23p
IO/LVDS19n
IO/LVDS19p
IO/LVDS18n
VCCIO2
IO/LVDS18p
GND
IO/LVDS17p
IO/LVDS17n/DEV CLRn
IO/LVDS16p
IO/LVDS16n
0 . 1
C5035
XX
L5007
1/10W
RN-CP
5%
10k
R5011
3.3V_MAIN
FPGA_2_LVDSTX
0 . 1
C5021
1000p
C5025
1uH
L5008
10
C5018
1000p
C5036
0 . 1
C5037
10
C5038
1uH
L5009
FPGA_RESETQ
VIDEO_VCTP_2_FPGA
CLKIN_2025
10
RB5009
10
RB5010
10
RB5011
10
RB5012
10
RB5015
10
RB5014
10
RB5013
10
RB5017
10
RB5016
SCL
SDA
R5022
100
R5023
100
JL5020
JL5021
JL5002
JL5003
5001
JL5004
R5009
XX
XX
R5018
JL5005
JL5006
JL5007
JL5010
JL5022
XX
C5048
47
R5013
100
R5019
0
R5060
XX
R5061
R5010
XX
CHIP
0
JR5007
XX
C5060
FPGA_NOT_BYPASS
TP5032
TP5033
GND_1
DGO2
DRO3
DRO2
DEN_OUT DEN_OUT
DVS_OUT DVS_OUT
DHS_OUT
DBO9
DBO8
DBO7
DBO6
DBO5
DBO4
DGO9
DGO8
DGO7
DGO6
DGO5
DGO4
DRO9
DRO8
DRO7
DRO6
GND_1
DRO5
GND_1
GND_1
PORT_A_A2_B2 PORT_A_A1_B1 PORT_A_A0_B0
PORT_A_DE
PORT_A_VSYNCPORT_A_VSYNC PORT_A_HSYNCPORT_A_HSYNC PORT_A_A3_B3 PORT_A_A4_B4 PORT_A_A5_B5 PORT_A_A6_B6 PORT_A_A8_B8
PORT_A_A9_B9
PORT_A_A7_B7
PORT_A_A13_G3
PORT_A_A12_G2
PORT_A_A11_G1
PORT_A_A10_G0
PORT_A_A14_G4
PORT_A_A15_G5
PORT_A_A16_G6
PORT_A_A17_G7
PORT_A_A19_G9
PORT_A_A20_R0
PORT_A_A21_R1
PORT_A_A18_G8
PORT_A_A25_R5
PORT_A_A24_R4
PORT_A_A23_R3
PORT_A_A22_R2
PORT_A_A28_R8
PORT_A_A26_R6
PORT_A_A27_R7
PORT_A_A29_R9
GND_1
DRO4
GND_1
PORT_A_CLKA1
GND_1
G
GNDA_PLL2
GNDA_PLL1
GND = BYP
VCC=NORMAL
Imax = 455mA
Imax = 455mA
6D/13
BC
BC.SE1A
~ BC Board Schematic Diagram [ Tuner, Audio/Video Processor, HDMI & PC Input ] Page 6D/13 ~