3.3V LVTTL I/O,5V-tolerance,
Motor Hall sensor input. The pin is spike-free at power-on
6 mA PDR,75K pull-up
stage.
N1
FEFMO
A
.
t
u
p
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u
o
C
A
D
.
l
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t
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c
1
r
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t
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m
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e
F
t
u
p
t
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O
g
o
l
a
n
N3
FEFMO2
A
.
t
u
p
t
u
o
C
A
D
.
l
o
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t
n
o
c
2
r
o
t
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m
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F
t
u
p
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O
g
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Feed motor 3 control. DAC output.
Alternative Function : Auxiliary servo input
Feed motor 4 control. DAC output.
Alternative Function : Auxiliary servo input
Input of Focusing Signal (Negative)
Alternative Function : Auxiliary servo input
Input of Focusing Signal (Positive)
Alternative Function : Auxiliary servo input
L3
FOO
A
.
r
o
t
a
s
n
e
p
m
o
c
o
v
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s
s
u
c
o
f
f
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t
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p
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M
D
P
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t
u
p
t
u
o
o
v
r
e
s
s
u
c
o
F
t
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p
t
u
O
g
o
l
a
n
D1
FPDOCD
A
t
u
p
n
i
e
v
i
t
a
g
e
n
l
a
i
t
n
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r
e
f
f
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D
/
C
P
A
D
C
r
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f
t
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I
r
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t
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o
M
r
e
w
o
P
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s
a
L
t
u
p
n
I
g
o
l
a
n
E2
FPDODVD
A
t
u
p
n
i
e
v
i
t
i
s
o
p
l
a
i
t
n
e
r
e
f
f
i
D
/
C
P
A
D
V
D
r
o
f
t
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p
n
I
r
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t
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o
M
r
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w
o
P
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s
a
L
t
u
p
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I
g
o
l
a
n
T1
FEGAINSW1
A
1
.
h
c
t
i
w
s
n
i
a
g
d
a
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R
t
u
p
t
u
O
g
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l
a
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P4
FEGAINSW2
A
.
2
h
c
t
i
w
s
n
i
a
g
d
a
e
R
t
u
p
t
u
O
g
o
l
a
n
P6
FEGAINSW3
A
.
3
h
c
t
i
w
s
n
i
a
g
d
a
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R
t
u
p
t
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O
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a
n
3.3V LVTTL I/O,5V-tolerance,
LDD serial interface data. The pin is spike-free at power-on
2,4,6,8 mA PDR,75K pulldown
stage. The pin is not allowed to pull-up in circuit layout.
FE_MUTE1
3.3V LVTTL I/O,5V-tolerance,
LDD serial interface CLK. The pin is spike-free at power-on
2,4,6,8 mA PDR,75K pulldown
stage. The pin is not allowed to pull-up in circuit layout.
FE_MUTE2
3.3V LVTTL I/O,5V-tolerance,
PC RS232 serial receive data. The pin is spike-free at poweron
2,4,6,8 mA PDR,75K pull-up
stage
URXD
3.3V LVTTL I/O,5V-tolerance,
PC RS232 serial transmit data. The pin is spike-free at poweron
2,4,6,8 mA PDR,75K pull-up
stage.
UTXD
3.3V LVTTL I/O,5V-tolerance,
High speed serial output port. (CLOCK) The pin is spike-free
2,4,6,8 mA PDR,75K pull-up
at power-on stage.
3.3V LVTTL I/O,5V-tolerance,
High speed serial output port (Data) The pin is spike-free at
2,4,6,8 mA PDR,75K pull-up
power-on stage.
3.3V LVTTL I/O,5V-tolerance,
General IO. The pin is spike-free at power-on stage.
2,4,6,8 mA PDR,75K pull-up
3.3V LVTTL I/O,5V-tolerance,
LED Control Output. Initial 0 Output. The pin is spike-free at
2,4,6,8 mA PDR,75K pull-up
power-on stage.
FE_EJECT
Read/Write gain switch 6
Read/Write gain switch 7
Read/Write gain switch 8. The pin is not allowed to pull-up in
circuit layout.
3.3V LVTTL I/O,5V-tolerance,
General IO. The pin is spike-free at power-on stage. The pin is
2,4,6,8 mA PDR,75K pulldown
not allowed to pull-up in circuit layout.
3.3V LVTTL I/O,5V-tolerance,
General IO The pin is spike-free at power-on stage.
2,4,6,8 mA PDR,75K pull-up
3.3V LVTTL I/O,5V-tolerance,
General IO. The pin is spike-free at power-on stage.
2,4,6,8 mA PDR,75K pulldown
Decoupling Pin for Reference Voltage of Main and Sub
Beams
G2
INA
Analog Input
Input of Main Beam Signal (A)
G1
INB
Analog Input
Input of Main Beam Signal (B)
o
l
a
n
A
C
N
I
2
H
g Input
Input of Main Beam Signal (C)
H1
IND
Analog Input
Input of Main Beam Signal (D)
K3
INE
Analog Input
Input of Sub-Beam Signal (E)
K4
INF
Analog Input
Input of Sub-Beam Signal (F)
J4
ING
Analog Input
Input of Sub-Beam Signal (G)
J3
INH
Analog Input
Input of Sub-Beam Signal (H)
Sledge Inner Limit Input, Active Low. The pin is spike-free at
power-on stage.
Multiplexer Output 1 for Signal Monitoring. The pin is not
allowed to pull-up in circuit layout.
Multiplexer Output 2 for Signal Monitoring. The pin is not
allowed to pull-up in circuit layout.
U2
FEGIO6
Analog Output
Analog Output
FEGIO4
T3
Analog Output
FEGIO5
U1
T2
FEGIO2
FEGIO3
T6
U6
FEGIO12
T5
FEGIO13
FEGIO10
U3
U5
FEGIO11
R4
FEGIO0
R6
FEGIO1
C1
FOIN Analog
Input
Analog Input
FOIP
C2
P1
FEFMO3
Analog I/O
N5
FEFMO4
Analog I/O
W5
FEFG
Analog Output
W3
FEGIO7
T4
FEGIO8
3.3V LVTTL I/O,5V-tolerance,
6 Ma,75k pull-up
V3
FEGIO9
P2
FEMPXOUT2
K5
HAVC
Analog Output
N6
FEMPXOUT1 Analog
Output
V4
FELIMIT_
BDP-S485
6-6
