SN8P2501D
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 78
Version 1.5
When buzzer outputs, TC0IRQ still actives as TC0 overflows, and TC0 interrupt function actives as TC0IEN = 1. But
strongly recommend be careful to use buzzer and TC0 timer together, and make sure both functions work well.
The buzzer output pin is shared with GPIO and switch to output buzzer signal as TC0OUT=1 automatically. If TC0OUT
bit is cleared to disable buzzer signal, the output pin exchanges to last GPIO mode automatically. It easily to implement
carry signal on/off operation, not to control TC0ENB bit.
Buzzer Output
TC0OUT=1. The pin exchanges to output
mode and outputs Buzzer signal
automatically.
TC0OUT=0. The pin exchanges
to last GPIO mode (output low).
TC0OUT=1.
TC0OUT=0.
Buzzer Output
TC0OUT=0. The pin exchanges
to last GPIO mode (output high).
TC0OUT=1.
TC0OUT=0.
Buzzer Output
TC0OUT=0. The pin exchanges
to last GPIO mode (input).
TC0OUT=1.
TC0OUT=0.
High impendence (floating)
TC0OUT=1. The pin exchanges to output
mode and outputs Buzzer signal
automatically.
TC0OUT=1. The pin exchanges to output
mode and outputs Buzzer signal
automatically.
Note: Because the TC0OUT decides the PWM cycle in PWM mode. The PWM0OUT bit must be
“0” when
buzzer output function works.
8.3.8 PULSE WIDTH MODULATION (PWM)
The PWM is duty/cycle programmable design to offer various PWM signals. When TC0 timer enables and PWM0OUT
bit sets as
“1” (enable PWM output), the PWM output pin (P5.4) outputs PWM signal. One cycle of PWM signal is high
pulse first, and then low pulse outputs. TC0rate[2:0] bits control the cycle of PWM, ALOAD0 and TC0OUT bits decides
the resolution of PWM, and TC0R decides the duty (high pulse width length) of PWM. TC0C initial value is zero when
TC0 timer enables and TC0 timer overflows. When TC0C count is equal to TC0R, the PWM high pulse finishes and
exchanges to low level. When TC0 overflows (TC0C counts from 0xFF to 0x00), one complete PW M cycle finishes.
The PWM exchanges to high level for next cycle. The PWM is auto-reload design to load TC0R when TC0 overflows
and the end of PWM
’s cycle, to keeps PWM continuity. If modify the PWM duty by program as PWM outputting, the
new duty occurs at next cycle when TC0R loaded from the reload buffer.
0x00
0x01
0x02
TC0C
...
TC0R
-1
TC0R
TC0R
+1
PWM Output
...
0xFD
0xFE
0xFF
0x00
0x01
0x02
...
Enable TC0 and PWM.
TC0C counts from 0x00.
PWM outputs high status.
TC0C = TC0R.
PWM exchanges to low status.
TC0C overflows from 0xFF to 0x00.
TC0C counts from 0x00.
PWM exchanges to high status.
One complete cycle of PWM.
Next cycle.