SONIX SN32F107, Руководство пользователя

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SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 108
Version 1.9
0 SSPEN
SSP enable bit
0: Disable
1: Enable.
R/W 0
10.6.2 SSP n Control register 1 (SSPn_CTRL1) (n=0, 1)
Address Offset: 0x04
Bit Name Description Attribute Reset
31:3 Reserved R 0
2 CPHA
Clock phase for edge sampling.
0: Data changes at clock falling edge, latches at clock rising edge when
CPOL = 0; Data changes at clock rising edge, latches at clock falling
edge when CPOL = 1.
1: Data changes at clock rising edge, latches at clock falling edge when
CPOL = 0; Data changes at clock falling edge, latches at clock rising
edge when CPOL = 1.
R/W 0
1 CPOL
Clock polarity selection bit
0: SCK idles at Low level.
1: SCK idles at High level.
R/W 0
0
MLSB
MSB/LSB selection bit
0: MSB transmit first.
1: LSB transmit first.
R/W 0
10.6.3 SSP n Clock Divider register (SSPn_CLKDIV) (n=0, 1)
Address Offset: 0x08
Bit Name Description Attribute Reset
31:8 Reserved R 0
7:0 DIV[7:0]
SSPn clock divider
0: SCK = SSPn_PCLK / 2
1: SCK = SSPn_PCLK / 4
2: SCK = SSPn_PCLK / 6
X: SCK = SSPn_PCLK / (2X+2)
R/W 0
10.6.4 SSP n Status register (SSPn_STAT) (n=0, 1)
Address Offset: 0x0C
Bit Name Description Attribute Reset
31:7 Reserved R 0
6 RXFIFOTHF
RX FIFO threshold flag
0: Data in RX FIFO ≤ RXFIFOTH
1: Data in RX FIFO > RXFIFOTH
R 0
5 TXFIFOTHF
TX FIFO threshold flag
0: Data in TX FIFO > TXFIFOTH
1: Data in TX
FIFO ≤ TXFIFOTH
R 1
4 BUSY
Busy flag.
0: SSP controller is idle.
1: SSP controller is transferring.
R 0
3 RX_FULL
RX FIFO full flag.
0: RX FIFO is NOT full.
1: RX FIFO is full.
R 0
2 RX_EMPTY
RX FIFO empty flag
0: RX FIFO is NOT empty.
1: RX FIFO is empty.
R 1
1 TX_FULL
TX FIFO full flag.
0: TX FIFO is NOT full.
1: TX FIFO is full.
R 0
0 TX_EMPTY
TX FIFO empty flag
0: TX FIFO is NOT empty. In Master mode, the transmitter will begin to
transmit automatically.
1: TX FIFO is empty.
R 1