Socket VMZV7, Руководство пользователя

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CMOS Setup Utility
3-12
PCI Dynamic Bursting
When Enabled, every write transaction goes to the write buffer. Burstable trans-
actions then burst on the PCI bus and nonburstable transactions do not.
The optional are:
Disabled (Default)
, Enabled
PCI Master 0 WS Write
When Enabled, writes to the PCI bus are executed with zero wait state.
The optional are:
Enabled (Default)
, Disabled
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions
cycles. Select Enabled to support compliance with PCI specification version 2.1.
The optional are: Enabled,
Disabled(Default)
PCI #2 Access #1 Retry
When disabled, PCI#2 will not be disconnected until access finishes (default).
When enable, PCI#2 will be disconnected if max retries are attempted without
success.
The optional are:
Disabled (Default)
, Enabled
Memory Parity / ECC Check
E nable adds a parity check to the boot-up memory tests. Select Enabled only if the
system DRAM Contains parity.
The optional are:
Disabled(Default)
, Enabled