Socket VMZV6 FLEX-ATX, Руководство пользователя

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CMOS Setup Utility
3-9
CMOS Setup Utility - Copyright (C) 1984-2000 Award Software
Advanced Chipset Features
Bank 0/1 DRAM Timing
SDRAM Cycle Length
DRAM Clock
Memory Hole
P2C/C2P Concurrency
Fast R-W Turn Around
System BIOS Cacheable
Video RAM Cacheable
Frame Buffer Size
Onchip USB
USB Keyboard Support
Onchip Sound
Onchip Modem
CPU to PCI Write Buffer
PCI Dynamic Bursting
PCI Master 0 WS Write
PCI Delay Transaction
PCI#2 Access #1 Retry
Memory Parity / ECC Check SDRAM 8/10ns
3
Host CLK
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8M
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Enter: Select F5 : Previous Values +/-/PU/PD: Value F10: Save
F6 : Fail-safe defaults Esc:Exit F1: General Help F7 : Optimized Defaults
Bank 0/1 DRAM Timing
This item allows you to select the value in this field, depending on whether the
board has paged DRAMs or EDO (extended data output) DRAMs.
The optional are:
SDRAM 8/10ns(Default)
, Normal, Medium, Fast, Turbo
SDRAM Cycle Length
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing. Do not reset this field from the default
value specified by the system designer.
The optional are:
3(Default)
, 2