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Hi-Speed USB Device Transceiver with UTMI Interface

Revision 1.7 (05-11-07)

8

SMSC USB3250

PRODUCT PREVIEW

 

Application Diagram

Figure 3 Application Diagram for 56-pin QFN Package

UTMI

USB

POWER

TXVALID

TXREADY

RXACTIVE

RXVALID

RXERROR

VALIDH

DATABUS16_8

XCVRSELECT

TERMSELECT

SUSPENDN

RESET

OPMODE 0
OPMODE 1

LINESTATE 0
LINESTATE 1

CLKOUT

DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7

DATA 8
DATA 9
DATA 10
DATA 11
DATA 12
DATA 13
DATA 14
DATA 15

XI

XO

DP

DM

VDDA1.8

VDD1.8
VDD1.8
VDD1.8
VDD1.8

VDDA3.3
VDDA3.3

VDD3.3
VDD3.3
VDD3.3

VSS
VSS
VSS
VSS
VSS

VSSA
VSSA
VSSA
VSSA

USB-B

GND

VDD3.3

1ΜΩ

12MHz 

Crystal

LOAD

LOAD

44
42
41
40
39
37
36
35

34
32
31
30
29
27
26
25

10

11

12

16
23
38
53

4
7

15
28
43

45
51
50
46
52
47
54

17
18

13
24

20
19

22
21

49

3

2

14
33
48
55
56

1
5
8
9

RBIAS

6

12K

Ω

VDD1.8

Voltage 

Regulator

VDD3.3

10uF

1uF

1uF

10uF

VDD1.8

Ferrite Bead

Ferrite Bead

10uF

Содержание USB3250

Страница 1: ...ecovery circuit SYNC and EOP generation on transmit packets and detection on receive packets NRZI encoding and decoding Bit stuffing and unstuffing with error detection Supports the USB suspend state...

Страница 2: ...s are available upon request SMSC products are not designed intended authorized or warranted for use in any life support or other application where product failure could cause or contribute to persona...

Страница 3: ...circuit protection of DP and DM lines is provided for USB compliance While transmitting data the PHY serializes data and generates SYNC and EOP fields It also performs needed bit stuffing and NRZI enc...

Страница 4: ...VDDA3 3 VSSA RBIAS VDDA3 3 VSSA XI XO VDDA1 8 SUSPENDN VSS VDD3 3 XCVRSELECT OPMODE 1 OPMODE 0 VDD1 8 VDD1 8 RESET DATA 15 DATA 14 DATA 13 VDD3 3 DATA 5 DATA 2 DATA 3 DATA 4 DATA 1 USB 2 0 USB3250 PH...

Страница 5: ...ensure that the 1 5k pull up on DP remains powered 0 Transceiver circuitry drawing suspend current 1 Transceiver circuitry drawing normal current CLKOUT Output Rising Edge System Clock This output is...

Страница 6: ...ing into the TX Holding Register on the rising edge of CLKOUT TXREADY is an acknowledgement to the SIE that the transceiver has clocked the data from the bus and is ready for the next transfer on the...

Страница 7: ...Data Pin Table 4 Biasing and Clock Oscillator Pins NAME DIRECTION ACTIVE LEVEL DESCRIPTION RBIAS Input N A External 1 bias resistor Requires a 12K resistor to ground Used for setting HS transmit curr...

Страница 8: ...0 DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 DATA 6 DATA 7 DATA 8 DATA 9 DATA 10 DATA 11 DATA 12 DATA 13 DATA 14 DATA 15 XI XO DP DM VDDA1 8 VDD1 8 VDD1 8 VDD1 8 VDD1 8 VDDA3 3 VDDA3 3 VDD3 3 VDD3 3 VDD3 3 V...

Страница 9: ...0 05 0 1 2 07 04 1 1 2 06 04 2 07 04 C JEDEC MO 220 1 O F 1 56 TERMINAL QFN 8x8m m BODY 0 5m m PITCH PACKAGE OUTLINE MO 56 QFN 8x8 SIDE VIEW 3 D VIEWS TOP VIEW 3 2 BOTTOM VIEW N O TES 1 ALL DIMENSION...

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