SMSC LAN9303, Руководство пользователя, Страница: 9 / 10

LAN9303 Evaluation Board User Manual
SMSC LAN9303
USER MANUAL
Revision 1.0 (05-28-09)
9
2.5.2 Port 0 Mode
Note 2.8 There are no default setting for this switch. Customers must choose the appropriate MII
mode as dictated by their application.
Note 2.9 The P0_MODE[2:0] settings are defined in Table 2.12 :
Table 2.11 Port 0 Mode Switches
SWITCH DESCRIPTION FUNCTION
S2-1 8-position DIP switch, position 1
Sets P0_MODE0 low when closed (on).
Otherwise, the signal is pulled-up internally.
( Note 2.8 , Note 2.9 )
S2-2 8-position DIP switch, position 2
Sets P0_MODE1 low when closed (on).
Otherwise, the signal is pulled-up internally.
( Note 2.8 , Note 2.9 )
S2-3 8-position DIP switch, position 3
Sets P0_MODE2 low when closed (on).
Otherwise, the signal is pulled-up internally.
( Note 2.8 , Note 2.9 )
S2-4 8-position DIP switch, position 4
Sets P0_MODE3 low when closed (on).
Otherwise, the signal is pulled-up internally.
This switch selects the duplex polarity strap
default for Port 0 as follows:
If the strap value is “0”, a “0” on P0_DUPLEX
indicates full duplex, while a “1” indicates
half-duplex.
If the strap value is “1”, a “1” on P0_DUPLEX
indicates full duplex, while a “0” indicates
half-duplex.
The default setting is open.
S2-[5:8] 8-position DIP switch, positions 5-8
Note: These switches are not used and
should be ignored.
Table 2.12 P0_MODE[2:0] Settings
S2-3 S2-2 S2-1 PORT 0 MODE SETTINGS
0 0 0 MII MAC Mode
0 0 1 MII PHY Mode
0 1 0 MII PHY Mode / 200Mbps / 12mA clock output
0 1 1 MII PHY Mode / 200Mbps / 16mA clock output
1 0 0 RMII PHY Mode / 12mA clock output
1 0 1 RMII PHY Mode / 16mA clock output
1 1 0 RMII PHY Mode / clock is input
1 1 1 RESERVED