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SMSC LAN91C111, Техническое описание

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10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

Revision 1.91 (08-18-08)

76

SMSC LAN91C111 REV C

DATASHEET

REM_FLT- Remote Fault Detect

‘1’ indicates a Remote Fault. Latches the ‘1’ condition and is cleared by reading this register or
resetting the PHY.

CAP_ANEG - AutoNegotiation Capable  

Indicates the ability (‘1’) to perform ANEG or not (‘0’).

LINK - Link Status 

A ‘1’ indicates a valid Link and a ‘0’ and invalid Link. The ‘0’ condition is latched until this register is
read.

JAB - Jabber Detect

Jabber condition detected when ‘1’ for 10Mbps. ‘1’ latched until this register is read or the PHY is reset.
Always ‘0’ for 100Mbps

EXREG - Extended Capability register

 ‘1’ Indicates extended registers are implemented

9.3

Register 2&3. PHY Identifier Register

These two registers (offsets 2 and 3) provide a 32-bit value unique to the PHY. 

9.4

Register 4. Auto-Negotiation Advertisement Register

This register control the values transmitted by the PHY to the remote partner when advertising its
abilities

REG

BITS

NAME

DEFAULT VALUE

R/W

SOFT RESET

2

15-0

Company ID

0000000000010110

R

Retains Original Value

3

15-10

Company ID

111110

R

Retains Original Value

3

9-4

Manufacturer's ID

000100

R

Retains Original Value

3

3-0

Manufacturer's Revision #

- - - -

R

Retains Original Value

NP

ACK

RF

Reserved

Reserved

Reserved

T4

TX_FDX

RW

R

RW

RW

RW

RW

RW

RW

0

0

0

0

0

0

0

1

TX_HDX

10_FDX

10_HDX

Reserved

Reserved

Reserved

Reserved

CSMA

RW

RW

RW

RW

RW

RW

RW

RW

1

1

1

0

0

0

0

1

Содержание LAN91C111

Страница 1: ...e 25 MHz Reference Clock for Both PHY and MAC External 25Mhz output pin for an external PHY supporting PHYs physical media Low Power CMOS Design Supports Multiple Embedded Processor Host Interfaces AR...

Страница 2: ...standard Terms of Sale Agreement dated before the date of your order the Terms of Sale Agreement The product may contain design defects or errors known as anomalies which may cause the product s funct...

Страница 3: ...21 7 5 2 Management Data Timing 22 7 5 3 MI Serial Port Frame Structure 22 7 5 4 MII Packet Data Communication with External PHY 24 7 6 Serial EEPROM Interface 25 7 7 Internal Physical Layer 25 7 7 1...

Страница 4: ...I Registers 70 9 1 Register 0 Control Register 74 9 2 Register 1 Status Register 75 9 3 Register 2 3 PHY Identifier Register 76 9 4 Register 4 Auto Negotiation Advertisement Register 76 9 5 Register 5...

Страница 5: ...10 100 Non PCI Ethernet Single Chip MAC PHY Datasheet SMSC LAN91C111 REV C 5 Revision 1 91 08 18 08 DATASHEET Chapter 15 Package Outlines 126 Chapter 16 Revision History 128...

Страница 6: ...TXEMPTY INTR Assumes Auto Release Option Selected 91 Figure 10 5 Drive Send and Allocate Routines 92 Figure 10 6 Interrupt Generation for Transmit Receive MMU 94 Figure 11 1 64 X 16 Serial EEPROM Map...

Страница 7: ...vents For Placing Device In Low Power Mode 84 Table 10 2 Flow Of Events For Restoring Device In Normal Power Mode 85 Table 12 1 VL Local Bus Signal Connections 98 Table 12 2 High End ISA or Non Burst...

Страница 8: ...ugh ISA cannot sustain 100 Mbps traffic Fast Ethernet data rates are attainable for ISA based nodes on the basis of the aggregate traffic benefits Two different interfaces are supported on the network...

Страница 9: ...2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Configuration nBE2 nBE1 nBE0 GND A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 VDD D8 D9 D10 D11 GND D12...

Страница 10: ...41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Configuration LAN91C111 FEASTTM 128 PIN QFP XTAL1 XTAL2 VDD nCSOUT IOS0 IOS1 IOS2 ENEEP EEDO EEDI EESK EECS AVDD RBIAS AGND...

Страница 11: ...h minimal Host and external supporting devices required to implement 10 100 Ethernet connectivity solutions The optional Serial EEPROM is used to store information relating to default IO offset parame...

Страница 12: ...bedded RISC and ARM processors The figure shown next page describes the SMSC LAN91C111 functional blocks required to integrate a 10 100 Ethernet Physical layer framer to the internal MAC Figure 3 2 Bl...

Страница 13: ...ODER SCRAMBLER TPO SWITCHED CURRENT SOURCE 100BASE TX TRANSMITTER CLOCK GEN PLL TPO LP FILTER TPI TPI LP FILTER Vth 10BASE T RECEIVER MLT3 ENCODER ADAPTIVE EQUALIZER Vth 100BASE TX RECEIVER MLT ENCODE...

Страница 14: ...A15 AEN nBE0 nBE3 20 System Data Bus D0 D31 32 System Control Bus RESET nADS LCLK ARDY nRDYRTN nSRDY INTR0 nLDEV nRD nWR nDATACS nCYCLE W nR nVLBUS 14 Serial EEPROM EEDI EEDO EECS EESK ENEEP IOS0 IOS...

Страница 15: ...upports direct connection to the system bus without external buffering For 16 bit systems only D0 D15 are used 30 32 Reset RESET IS Input When this pin is asserted high the controller performs an inte...

Страница 16: ...8 nReady Return nRDYRTN I Input This input is used to complete synchronous read cycles In EISA burst mode it is sampled on falling LCLK edges and synchronous cycles are delayed until it is sampled hig...

Страница 17: ...tal is connected across these pins If a TTL clock is supplied instead it should be connected to XTAL1 and XTAL2 should be left open XTAL1 is the 5V tolerant input of the internal amplifier and XTAL2 i...

Страница 18: ...management data input 26 28 Management Data Output MDO O4 MII management data output 27 29 Management Clock MCLK O4 MII management clock 126 128 Receive Error RX_ER I with pulldown Input Indicates a...

Страница 19: ...a signal is inactive The term High Z means tri stated The term Undefined means the signal could be high low tri stated or in some in between level 6 1 Buffer Types DC levels and conditions defined in...

Страница 20: ...increase the bandwidth into memory a 50 MHz clock is used by the DMA block and the data path is 32 bits wide For example during active reception at 100 Mbps the CSMA CD block will write a word into th...

Страница 21: ...nction of A1 is implemented for 16 bit bus support f The asynchronous interface uses nRD and nWR strobes If necessary ARDY is negated on the leading edge of the strobe The ARDY trailing edge is contro...

Страница 22: ...on whether a write or read cycle was selected with the bits READ and WRITE After the 32 MDC cycles have been completed one complete register has been read written the serial shift process is halted da...

Страница 23: ...11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ST 1 0 OP 1 0 PHYAD 4 0 REGAD 4 0 TA 1 0 DATA 15 0 WRITE BITS PHY CLOCKS IN DATA ON RISING EDGES OF MDC WRITE CYCLE MDIO MDC 0 2 1 3 4 7 6 5 8 9 10 11 12 13 14 15...

Страница 24: ...D0 TXD3 having the first valid preamble nibble TXD0 carries the least significant bit of the nibble that is the one that would go first out of the EPH at 100 Mbps while TXD3 carries the most significa...

Страница 25: ...Bus of the LAN91C111 during active operation 7 7 Internal Physical Layer The LAN91C111 integrates the IEEE 802 3 physical layer PHY internally The EXT PHY bit in the Configuration Register is 0 as th...

Страница 26: ...LT 3 coded twisted pair levels to internal digital levels The output of the twisted pair receiver then goes to a clock and data recovery block which recovers a clock from the incoming data uses the cl...

Страница 27: ...ed in IEEE 802 3 The 4B5B encoder also fills the period between packets called the idle period with the continuous stream of idle symbols Manchester Encoder 10 Mbps The Manchester encoding process com...

Страница 28: ...and the second half of the data bit contains the true data The Manchester decoder in the LAN91C111 converts the Manchester encoded data stream from the TP receiver into NRZ data for the controller int...

Страница 29: ...symbols to pass at least 6 nibbles of preamble to the receive controller interface as shown in Figure 7 2 Data Recovery 10 Mbps The data recovery process for 10Mbps mode is identical to the 100Mbps mo...

Страница 30: ...components In this way the waveform generator preshapes the output waveform transmitted onto the twisted pair cable to meet the pulse template requirements outlined in IEEE 802 3 The waveform generat...

Страница 31: ...mplate 10 MBPS REFERENCE TIME NS INTERNAL MAU VOLTAGE V A 0 0 B 15 1 0 C 15 0 4 D 25 0 55 E 32 0 45 F 39 0 G 57 1 0 H 48 0 7 I 67 0 6 J 89 0 K 74 0 55 L 73 0 55 M 61 0 N 85 1 0 O 100 0 4 P 110 0 75 0...

Страница 32: ...as shown in Table 7 2 The adjustment range is approximately 14 to 16 in 2 steps Transmit Rise and Fall Time Adjust The transmit output rise and fall time can be adjusted with the two transmit rise fal...

Страница 33: ...X receiver consists of an adaptive equalizer baseline wander correction circuit comparators and MLT 3 decoder The TP inputs first go to an adaptive equalizer The adaptive equalizer compensates for the...

Страница 34: ...input signal is deemed to be valid The device stays in the unsquelch state until loss of data is detected Loss of data is detected if no alternating polarity unsquelch transitions are detected during...

Страница 35: ...s performed 4 MAC is notified of the collision when the jabber condition has been detected Collision Test The MAC and PHY collision indication can be tested by setting the collision test register bit...

Страница 36: ...of the transmit data packet The receive ESD pattern is detected by the 4B5B decoder by examining groups of 10 consecutive code bits two 5B words from the descrambler during valid packet reception to...

Страница 37: ...om a remote device The standard link integrity and AutoNegotiation algorithms are described below AutoNegotiation is only specified for 100BASE TX and 10BASE T operation 10BASE T Link Integrity Algori...

Страница 38: ...tion algorithm is used for two purposes 1 To automatically configure the device for either 10 100 Mbps and Half Full Duplex modes and 2 to establish an active link to and from a remote device The Auto...

Страница 39: ...ed in IEEE 802 3 Clause 28 Once the negotiation process is completed the LAN91C111 then configures itself for either 10 or 100 Mbps mode and either Full or Half Duplex modes depending on the outcome o...

Страница 40: ...disabled the device is forced into the Link Pass state configures itself for Half Full Duplex based on the value of the duplex bit in the PHY MI serial port Control register configures itself for 100...

Страница 41: ...PHY MI serial port Control register assuming AutoNegotiation is not enabled The device can automatically configure itself for 100 or 10 Mbps mode by using the AutoNegotiation algorithm to advertise a...

Страница 42: ...l registers to their default value When reset is initiated by 1 and the EEPROM is presented and enabled the controller will load the EEPROM to obtain the following configurations 1 Configuration Regis...

Страница 43: ...nes the total number of words including the STATUS WORD the BYTE COUNT WORD the DATA AREA the CRC and the CONTROL BYTE The CRC is not included if the STRIP_CRC bit is set The maximum number of bytes i...

Страница 44: ...preted by the LAN91C111 It is treated transparently as data both for transmit and receive operations CONTROL BYTE For transmit packets the CONTROL BYTE is written by the CPU as ODD If set indicates an...

Страница 45: ...hash value corresponds to a multicast table bit that is set and the address was a multicast the packet will pass address filtering regardless of other filtering criteria 8 3 I O Space The base I O spa...

Страница 46: ...doubleword write to offset 0x0Ch will write the BANK SELECT REGISTER but will not write the registers 0x0Ch and 0x0Dh but will only write to register 0x0Eh BANK 7 has no internal registers other than...

Страница 47: ...tes the SQET pulse during the IPG Inter Frame Gap this bit will not be set and subsequent transmits will occur as in the case of implementing Auto Release for multiple transmit packets If this bit is...

Страница 48: ...ansmissions The register can be used for real time values like TXENA and LINK OK If TXENA is cleared the register holds the last packet completion status LINK_OK General purpose input port driven by n...

Страница 49: ...etected for the last transmit frame Set when a collision is detected Cleared when TX_SUC is high at the end of the packet being sent TX_SUC Last transmit was successful Set if transmit completes witho...

Страница 50: ...Reserved Must be 0 8 8 Bank 0 Counter Register Counts four parameters for MAC statistics When any counter reaches 15 an interrupt is issued All counters are cleared when reading the register and do n...

Страница 51: ...t 1 the Internal PHY will operate at 100Mbps When this bit is cleared 0 the Internal PHY will operate at 10Mbps When the ANEG bit 1 this bit is ignored and 10 100 operation is determined by the outcom...

Страница 52: ...s placed in manual mode WHAT DO YOU WANT TO DO AUTO NEGOTIATION CONTROL BITS AUTO NEGOTIATION ADVERTISEMENT REGISTER DUPLEX MODE CONTROL FOR THE MAC Try to Auto Negotiate to ANEG Bit ANEG_E N Bit TX_F...

Страница 53: ...AL LEDA 0 0 0 nPLED3 nPLED0 Logical OR of 100Mbps Link detected 10Mbps Link detected default 0 0 1 Reserved 0 1 0 nPLED0 10Mbps Link detected 0 1 1 nPLED1 Full Duplex Mode enabled 1 0 0 nPLED2 Transmi...

Страница 54: ...additional wait states An exception to this are accesses to the Data Register if not ready for a transfer When clear negates ARDY for two to three clocks on any cycle to the LAN91C111 GPCNTRL This bit...

Страница 55: ...e I O base decode defaults to 300h namely the high byte defaults to 18h Reserved Reserved bits Below chart shows the decoding of I O Base Address 300h 8 13 Bank 1 Individual Address Registers These re...

Страница 56: ...the Individual Address area of the EEPROM that is normally protected from accidental Store operations This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Contro...

Страница 57: ...edge the interrupt CR ENABLE defaults low disabled TE ENABLE Transmit Error Enable When set it enables Transmit Error as one of the interrupts merged into the EPH INT bit An EPH INT interrupt caused b...

Страница 58: ...PU has completed processing of present receive frame This command removes the receive packet number from the RX FIFO and brings the next receive frame if any to the RX area output of RX FIFO 100 4 REM...

Страница 59: ...MMU command register address When set indicates that MMU is still processing a release command When clear MMU has already completed last release command BUSY and FAILED bits are set upon the trailing...

Страница 60: ...ns the value read from the ARR after an allocation request is intended to be written into the PNR as is without masking higher bits provided FAILED 0 8 18 Bank 2 FIFO Ports Register This register prov...

Страница 61: ...f access to follow If the READ bit is high the operation intended is a read If the READ bit is low the operation is a write Loading a new pointer value with the READ bit high generates a pre fetch int...

Страница 62: ...the Data Low or Data High registers The order to and from the FIFO is preserved Byte word and dword accesses can be mixed on the fly in any order This register is mapped into two consecutive word loc...

Страница 63: ...ved Must be 0 EPH INT Set when the Ethernet Protocol Handler section indicates one out of various possible special conditions This bit merges exception type of interrupt sources whose service time is...

Страница 64: ...OCATION RESULT register The ALLOC INT bit is cleared by the MMU when the next allocation request is processed or allocation fails TX EMPTY INT Set if the TX FIFO goes empty can be used to generate a s...

Страница 65: ...X_OVRN MDINT nWRACK TX Complete Fatal TX Error SQET LOST CARR LATCOL 16COL Interrupt Status Register 7 6 5 4 3 2 1 0 nRDIST Interrupt Mask Register 7 6 5 4 3 2 1 0 OE nOE Edge Detector on Link Err LEM...

Страница 66: ...less of the multicast table values Hashing is only a partial group addressing filtering scheme but being the hash value available as part of the receive status word the receive routine can reduce the...

Страница 67: ...hen high pin MDO is driven when low pin MDO is tri stated The purpose of this interface along with the corresponding pins is to implement MII PHY management in software 8 24 Bank 3 Revision Register C...

Страница 68: ...cket was discarded Otherwise the packet will be received normally and bit 0 set RCVINT in the interrupt status register RCV DISCRD is self clearing MBO Must be 1 8 26 Bank 7 External Registers nCSOUT...

Страница 69: ...Revision 1 91 08 18 08 DATASHEET CYCLE NCSOUT LAN91C111 DATA BUS AEN 0 A3 0 A4 15 matches I O BASE BANK SELECT 7 Driven low Transparently latched on nADS rising edge Ignored on writes Tri stated on re...

Страница 70: ...state Another serial shift cycle cannot be initiated until the idle condition at least 32 continuous 1 s is detected Bit Types Since the serial port is bi directional there are many types of bits Wri...

Страница 71: ...Mask Register 20 Reserved 17 Configuration 2 18 Status Output 19 Mask 20 Reserved Table 9 1 MII Serial Frame Structure Idle Start Read Write PHY Addr REG Addr Turnaround Data IDLE ST 1 0 READ WRITE PH...

Страница 72: ...ime is a 2 bit time spacing between the Register Address field and the Data field of a management frame to avoid contention during a read transaction For a read transaction both the STA and the PHY sh...

Страница 73: ...R W R R W R W 1 0 0 0 0 0 0 0 0 1 1 0 0 0 10_FDX TX_HDX TX_FDX T4 RF NP ACK 10_HDX CSMA R R R R R R R R 0 0 R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 RLVL0 CABLE EQLZR UNSCDS XMTPDN LNKDIS XMTDIS Res...

Страница 74: ...is 1 In that case the contents of bits Speed and Duplex are ignored and the ANEG process determines the link configuration PDN Power down Setting this bit to 1 will put the PHY in PowerDown mode In th...

Страница 75: ...ASE TX Half Duplex Capable 1 Indicates 100Base X alf duplex capable PHY 0 not capable CAP_TF 10BASE T Full Duplex Capable 1 Indicates 10Mbps full duplex capable PHY 0 not capable CAP_TH 10BASE T Half...

Страница 76: ...ended Capability register 1 Indicates extended registers are implemented 9 3 Register 2 3 PHY Identifier Register These two registers offsets 2 and 3 provide a 32 bit value unique to the PHY 9 4 Regis...

Страница 77: ...SE TX Half Duplex Capable A 1 indicates the PHY is capable of 100BASE TX Half Duplex 10_FDX 10BASE T Full Duplex Capable A 1 indicates the PHY is capable of 10BASE T Full Duplex 10_HDX 10BASE T Half D...

Страница 78: ...led Force Link Pass 0 Normal XMTDIS TP Transmit 1 TP Transmitter Disabled 0 Normal XMTPDN TP Transmit 1 TP Transmitter Powered Down Powerdown 0 Normal RESERVED RESERVED Reserved Must be 0 for Proper O...

Страница 79: ...2 Level Adjust TRF0 1 Transmitter 11 0 25nS Rise Fall Time 10 0 0nS Adjust 01 0 25nS 00 0 50nS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R R R R R R R R 1 1 1 1 1 1 1 1...

Страница 80: ...IO 0 Interrupt Not Signaled On MDIO Reserved Reserved for Factory Use INT LNKFAIL LOSSSYNC CWRD SSD ESD RPOL JAB R R LT R LT R LT R LT R LT R LT R LT 0 0 0 0 0 0 0 0 SPDDET DPLXDET Reserved Reserved R...

Страница 81: ...1 Reverse Polarity Detected JAB Jabber Detect 1 Jabber Detected 0 Normal SPDDET 100 10 Speed Detect 1 Device in 100Mbps Mode 100BASE TX 0 Device in 10Mbps Mode 10BASE T DPLXDET Duplex Detect 1 Device...

Страница 82: ...ask Start Of Stream Error 1 Mask Interrupt For SSD In Register 18 0 No Mask MESD Interrupt Mask End Of Stream Error 1 Mask Interrupt For ESD In Register 18 0 No Mask MRPOL Interrupt Mask Reverse Polar...

Страница 83: ...le Chip MAC PHY Datasheet SMSC LAN91C111 REV C 83 Revision 1 91 08 18 08 DATASHEET Reserved Reserved for Factory Use Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RW RW RW RW...

Страница 84: ...e TXENA bit of the Transmit Control Register Ethernet MAC finishes packet currently being transmitted 2 Remove and release all TX completion packet numbers on the TX completion FIFO 3 Disable Receiver...

Страница 85: ...transmit Ethernet Packets 8 Enable Receiver Set 1 the RXEN bit of the Receive Control Register Ethernet MAC is now able to receive Packets 9 Ethernet MAC is now restored for normal operation S W DRIVE...

Страница 86: ...ing TX INT Acknowledge Register Option 1 Release the packet Option 2 Check the transmit status in the EPH STATUS Register write the packet number of the current packet to the Packet Number Register re...

Страница 87: ...is requested if more pages are needed 3 The internal DMA logic generates sequential addresses and writes the receive words into memory The MMU does the sequential to physical address translation If o...

Страница 88: ...MPTY INTR TX INTR Get Next TX RX INTR Yes No No Yes Call RXINTR ALLOC INTR No Yes Write Allocated Pkt into Packet Number Reg Write Ad Ptr Reg Copy Data Source Address Enqueue Packet Packet Available f...

Страница 89: ...R RX INTR Write Ad Ptr Reg Read Word 0 from RAM Destination Multicast Read Words 2 3 4 from RAM for Address Filtering Address Filtering Pass Status Word OK Do Receive Lookahead Get Copy Specs from Upp...

Страница 90: ...ease Specific Packet Write 0x00A0 Bank2 Offset 0 Step 4 1 2 Return from the routine else Transmission has FAILED Now we can either release or re enqueue the packet Step 4 2 1 Get the packet to release...

Страница 91: ...owledge Reg with TXEMPTY Bit Set Read TXEMPTY TX INTR Acknowledge TXINTR Re Enable TXENA Return to ISR Issue Release Command Restore Packet Number TXEMPTY 0 TXINT 0 Waiting for Completion TXEMPTY X TX...

Страница 92: ...it but it cannot determine the number of bytes the receive process is going to demand Furthermore the receive process requests will be dependent on network traffic in particular on the arrival of broa...

Страница 93: ...pt one packet at a time Depending on the completion code the driver will take different actions Note that the transmit process is working in parallel and other transmissions might be taking place The...

Страница 94: ...r Transmit Receive MMU TX FIFO TX COMPLETION FIFO RX FIFO CSMA CD LOGICAL ADDRESS PACKET MMU PHYSICAL ADDRESS RAM CPU ADDRESS CSMA ADDRESS RX PACKET NUMBER RX FIFO PACKET NUMBER PACKET NUMBER REGISTER...

Страница 95: ...default if the EEPROM read operation follows hardware reset The EEPROM SELECT bit is used to determine the type of EEPROM operation a normal or b general purpose register 1 NORMAL EEPROM OPERATION EEP...

Страница 96: ...PROM operation completes and both bits are clear This mechanism is also valid for reset initiated reloads Note If no EEPROM is connected to the LAN91C111 for example for some embedded applications the...

Страница 97: ...EEPROM Map CONFIGURATION REG BASE REG CONFIGURATION REG BASE REG CONFIGURATION REG BASE REG CONFIGURATION REG BASE REG CONFIGURATION REG BASE REG CONFIGURATION REG BASE REG CONFIGURATION REG BASE REG...

Страница 98: ...use byte word or dword instructions Table 12 1 VL Local Bus Signal Connections VL BUS SIGNAL LAN91C111 SIGNAL NOTES A2 A15 A2 A15 Address bus used for I O space and register decoding latched by nADS...

Страница 99: ...override the value of A1 which is tied low in this application nLDEV nLDEV nLDEV is a totem pole output nLDEV is active on valid decodes of A15 A4 and AEN 0 UNUSED PINS VCC nRD nWR GND A1 nVLBUS OPEN...

Страница 100: ...igh End ISA or Non Burst EISA Machines Signal Connectors ISA BUS SIGNAL LAN91C111 SIGNAL NOTES A1 A15 A1 A15 Address bus used for I O space and register decoding AEN AEN Qualifies valid I O decoding e...

Страница 101: ...0 nSBHE nBE1 IRQn INTR0 D0 D15 D0 D15 16 bit data bus The bus byte s used to access the device are a function of nBE0 and nBE1 Not used tri state on reads ignored on writes nIOCS16 nLDEV buffered nLDE...

Страница 102: ...transfers and is able to sustain the peak rate of one doubleword every BCLK Doubleword alignment is assumed for DMA transfers The LAN91C111 will sample EXRDY and postpone DMA cycles if the memory cycl...

Страница 103: ...enerate them nEX32 nNOWS optional additional logic nLDEV nLDEV is a totem pole output nLDEV is active on valid decodes of LAN91C111 pins A15 A4 and AEN 0 nNOWS is similar to nLDEV except that it shoul...

Страница 104: ...ET GND A1 Figure 12 3 LAN91C111 on EISA BUS Table 12 3 EISA 32 Bit Slave Signal Connections continued EISA BUS SIGNAL LAN91C111 SIGNAL NOTES A2 A15 RESET AEN INTR0 nRD nWR LCLK nADS nLDEV LAN91C111 LA...

Страница 105: ...s switched on or off In addition voltage transients on the AC power line may appear on the DC output If this possibility exists it is suggested that a clamp circuit be used 13 2 DC Electrical Characte...

Страница 106: ...VOH IOL 2 4 10 0 4 10 V V A IOL 6 mA IOH 4 mA VIN 0 to VCC I O4 Type Buffer Low Output Level High Output Level Output Leakage VOL VOH IOL 2 4 10 0 4 10 V V A IOL 6 mA IOH 4 mA VIN 0 to VCC O12 Type Bu...

Страница 107: ...age VOL VOH IOL 2 4 10 0 4 10 V V A IOL 4 mA na VIN 0 to VCC Supply Current Active ICC 100 140 mA Dynamic Current Assuming internal PHY is used Powerdown Supply Current IPDN 15 38 mA Internal PHY in P...

Страница 108: ...Differential Output Rise And Fall Time Symmetry 0 5 nS 100 Mbps Difference Between Rise and Fall Times on TPO ToDC TP Differential Output Duty Cycle Distortion 0 25 nS 100 Mbps Output Data 0101 NRZ Pa...

Страница 109: ...ve to Output with TLVL 3 0 1000 TOR TP Output Resistance 10K Ohm TOC TP Output Capacitance 15 pF SYM PARAMETER LIMIT UNIT CONDITIONS MIN TYP MAX RST TP Input Squelch Threshold 166 500 mV pk 100 Mbps R...

Страница 110: ...UNITS t1 A1 A15 AEN nBE 3 0 Valid to nRD nWR Active 2 ns t2 A1 A15 AEN nBE 3 0 Hold After nRD nWR Inactive Assuming nADS Tied Low 5 ns t3 nRD Low to Valid Data 15 ns t4 nRD High to Data Invalid 2 15 n...

Страница 111: ...e 2 ns t3 nRD Low to Valid Data 15 ns t4 nRD High to Data Invalid 2 15 ns t5 Data Setup to nWR Inactive 10 ns t5A Data Hold After nWR Inactive 5 ns t6 nRD Strobe Width 15 ns t8 A1 A15 AEN nBE 3 0 Setu...

Страница 112: ...ming nADS Tied Low 5 ns t3A nRD Low to Valid Data 30 ns t4 nRD High to Data Invalid 2 15 ns t5 Data Setup to nWR Inactive 10 ns t5A Data Hold After nWR Inactive 5 ns t6A nRD Strobe Width 30 ns Figure...

Страница 113: ...NITS t12 nDATACS Setup to LCLK Rising 20 ns t12A nDATACS Hold After LCLK Rising 0 ns t14 nRDYRTN Setup to LCLK Falling 10 ns t15 nRDYRTN Hold after LCLK Falling 10 ns t17 W nR Setup to LCLK Falling 15...

Страница 114: ...UNITS t12 nDATACS Setup to LCLK Rising 20 ns t12A nDATACS Hold after LCLK Rising 0 ns t14 nRDYRTN Setup to LCLK Falling 10 ns t15 nRDYRTN Hold after LCLK Falling 10 ns t17 W nR Setup to LCLK Falling 1...

Страница 115: ...ETER MIN TYP MAX UNITS t8 A1 A15 AEN nBE 3 0 Setup to nADS Rising 8 ns t9 A1 A15 AEN nBE 3 0 Hold After nADS Rising 5 ns t25 A4 A15 AEN to nLDEV Delay 30 ns Figure 14 8 Synchronous Write Cycle nVLBUS...

Страница 116: ...up to LCLK Rising 5 ns t11 nCYCLE Hold after LCLK Rising Non Burst Mode 3 ns t16 W nR Setup to nCYCLE Active 0 ns t17A W nR Hold after LCLK Rising with nSRDY Active 3 ns t18 Data Setup to LCLK Rising...

Страница 117: ...sing Non Burst Mode 3 ns t16 W nR Setup to nCYCLE Active 0 ns t20 Data Hold from LCLK Rising Read 4 ns t21 nSRDY Delay from LCLK Rising 7 ns t23 nRDYRTN Setup to LCLK Rising 3 ns t24 nRDYRTN Hold afte...

Страница 118: ...able 14 1 Transmit Timing Characteristics SYM PARAMETER LIMIT UNIT CONDITIONS MIN TYP MAX t30 Transmit Propagation Delay 60 140 nS 100Mbps 600 nS 10Mbps t31 Transmit Output Jitter 0 7 nS pk pk 100Mbps...

Страница 119: ...sure TPI from last zero cross to 0 3V point Figure 14 12 Receive Timing End of Packet 10 MBPS Table 14 3 Collision and Jam Timing Characteristics SYM PARAMETER LIMIT UNIT CONDITIONS MIN TYP MAX t38 Rc...

Страница 120: ...TASHEET Figure 14 13 Collision Timing Receive t34 LEDn t35 t34 t35 LEDn TPI I TPO I DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA I K J I I DATA I I R T DATA DATA DATA DATA DATA t 38 MII 100...

Страница 121: ...TASHEET Figure 14 14 Collision Timing Transmit t34 t35 t34 t35 LEDn LEDn TPO I TPI I DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA I K J I I DATA I I R T DATA DATA DATA DATA DATA t 39 MII 100...

Страница 122: ...122 SMSC LAN91C111 REV C DATASHEET Figure 14 15 Jam Timing t 41 t 40 MII 100 Mbps MII 10 Mbps TPI TPO I I DATA DATA DATA DATA K J DATA DATA TPO I I JAM I I R JAM JAM K JAM I I I J T I DATA DATA DATA...

Страница 123: ...nterval_timer t50 FLP Transmit Clock Pulse to Clock Pulse Period 111 125 139 S t51 FLP Transmit Link Pulse Burst Period 8 22 mS transmit_link_burst_time r t52 FLP Receive Link Pulse Width Required For...

Страница 124: ...Non PCI Ethernet Single Chip MAC PHY Datasheet Revision 1 91 08 18 08 124 SMSC LAN91C111 REV C DATASHEET Figure 14 16 Link Pulse Timing TPO t 42 a Transmit NLP t 43 TPI t 44 b Receive NLP t 45 t 47 t...

Страница 125: ...n 1 91 08 18 08 DATASHEET Figure 14 17 FLP Link Pulse Timing TPO t 48 a Transmit FLP and Transmit FLP Burst t 49 TPI t 52 b Receive FLP t 54 TPI CLK DATA CLK DATA DATA CLK CLK t 51 CLK DATA DATA CLK t...

Страница 126: ...S 026 dimension S of a minimum of 0 20mm Figure 15 1 128 Pin TQFP Package Outline 14X14X1 0 Body Table 15 1 128 Pin TQFP Package Parameters MIN NOMINAL MAX REMARK A 1 20 Overall Package Height A1 0 05...

Страница 127: ...15 2 128 Pin QFP Package Outline 3 9 MM Footprint Table 15 2 128 Pin QFP Package Parameters MIN NOMINAL MAX REMARKS A 3 4 Overall Package Height A1 0 05 0 5 Standoff A2 2 55 3 05 Body Thickness D 23...

Страница 128: ...ank 3 Revision Register on page 67 Changed REV default from 0001 to 0010 Rev 1 9 07 17 08 Table 14 3 Asynchronous Cycle nADS 0 on page 112 Changed T1A time in table under figure from 10nS min to 2nS m...

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