SMART 6806800K30J, Инструкция по установке и использованию

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Functional Description
RTM-ATCA-F125 Installation and Use (6806800K30J) 43
The RS0 and RS1 rate select signals from each SFP+ are individually connected to the
RTM FPGA that allows them to be controlled by software. Refer to
Section 4.6, FPGA on
page 43
for further details.
4.5 GPS Connectors
The 1PPS, 10MHz, and TOD inputs for connection to an external GPS receiver are not
supported at present.
4.6 FPGA
The RTM-ATCA-F125 includes a Xilinx XC3S200A-4 FPGA that which performs the
following functions:

Access to control and status signals on SFP and SFP+ sites

Access to control and status signals on the two BCM8747s

Provision of I2C interfaces to SFP sites

Reset handling

SPI Flash programmer and multiplexing for BCM8747 configuration

UART with selectable outputs for the optional GPS receiver (functionality not
initially implemented)
4.6.1 Front-blade Interface
The RTM-ATCA-F125 includes an SPI interface between the front-blade service processor
and the RTM FPGA. There is also an active low interrupt line to the front-blade to request
service.
4.6.2 SFP/SFP+ Control and Status
The RTM FPGA provides register access to control the following SFP and SFP+ signals:

SFP TX_DISABLE

SFP RATE_SEL

SFP+ RS0/1
The RTM FPGA provides access to the following SFP and SFP+ status signals:

SFP MOD_ABS

SFP TX_FAULT