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MVME4100 Single Board Computer Programmer’s Reference (6806800H19D)

Chapter 2

Memory Maps

2.1

Overview

The following sections describe the memory maps for the MVME4100. Refer to the

MPC8548E Reference Manual

for additional details and/or programming information.

2.1.1

Default Processor Memory Map

The following table describes a default memory map from the point of view of the processor

after a processor reset.

2.1.2

Suggested Processor Memory Map

The following table describes a suggested physical memory map from the point of view of

the processor. This table reflects the address map implemented by the board level firmware
at release time.

Table 2-1

Default Processor Address Map

Processor Address

Size

Definition

Notes

Start

End

0000 0000

FF6F FFFF

4087 M

Not mapped

FF70 0000

FF7F FFFF

1 M

MPC8548E CCSR
Registers

FF80 0000

FFFF FFFF

8 M

Flash

1. The e500 core fetches the first instruction from FFFF FFFC following a reset.

Table 2-2

Suggested Processor Address Map

Processor Address

Size

Definition

Start

End

0000 0000

top_dram - 1

dram_size

(2 GB max)

System Memory

(on-board DRAM)

8000 0000

CFFF FFFF

1.25 GB

PCI 0 Memory Space / VME

D000 0000

DFFF FFFF

256 MB

PCI 1 Memory Space

E000 0000

EFFF FFFF

256 MB

Not used

F000 0000

F07F FFFF

8 MB

PCI 0 I/O Space

Содержание MVME4100

Страница 1: ...MVME4100 Single Board Computer Programmer s Reference P N 6806800H19D September 2019 ...

Страница 2: ...r to the products described therein at any time without notice SMART EC makes no commitment to update the information contained within these materials Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to a SMART EC website The text itself may not be published commercially in print or electronic form edited translated or o...

Страница 3: ...atus Register 26 3 1 2 System Control Register 27 3 1 3 Status Indicator Register 28 3 1 4 NOR Flash Control Status Register 29 3 1 5 Interrupt Register 1 30 3 1 6 Interrupt Register 2 31 3 1 7 Presence Detect Register 32 3 1 8 PCI Bus Status Registers 32 3 1 9 NAND Flash Chip 1 Control Register 34 3 1 10 NAND Flash Chip 1 Select Register 35 3 1 11 NAND Flash Chip 1 Presence Register 36 3 1 12 NAN...

Страница 4: ...Programming Details 47 4 1 Overview 47 4 2 MPC8548E Reset Configuration 47 4 3 MPC8548E Interrupt Controller 54 4 4 Local Bus Controller Chip Select Assignments 55 4 5 I2C Device Addresses 56 4 6 User Configuration EEPROM 56 4 7 VPD EEPROM 57 4 8 RTM VPD EEPROM 57 4 9 Ethernet PHY Address 57 4 10 Flash Memory 58 4 11 PCI PCI X Configuration 58 4 11 1 PCI IDSEL and Interrupt Definition 59 4 11 2 PC...

Страница 5: ...and Modify VPD Information 66 A 5 What Happens if VPD Information is Corrupted 66 A 6 How to Fix Corrupted VPD Information 67 A 7 What if Your Board Has the Wrong VPD 67 A 8 How to Fix Wrong VPD Problems 67 A 9 Vital Product Data CRC Calculation 67 A 10 VPD Contents for MVME4100 Boards 69 B Related Documentation 79 B 1 SMART Embedded Computing Documentation 79 B 2 Manufacturers Documents 79 B 3 Re...

Страница 6: ...6 MVME4100 Single Board Computer Programmer s Reference 6806800H19D Table of Contents ...

Страница 7: ...List of Figures MVME4100 Single Board Computer Programmer s Reference 6806800H19D 7 Figure 1 1 Block Diagram 18 Figure 3 1 Boot Flash Bank 30 ...

Страница 8: ...8 MVME4100 Single Board Computer Programmer s Reference 6806800H19D Table of Contents ...

Страница 9: ...atus Register 34 Table 3 12 NAND Flash Chip 1 Control Register 34 Table 3 13 NAND Flash Chip 1 Select Register 35 Table 3 14 NAND Flash Chip 1 Presence Register 36 Table 3 15 NAND Flash Chip 1 Status Register 36 Table 3 16 NAND Flash Chip 2 Control Register 37 Table 3 17 NAND Flash Chip 2 Select Register 37 Table 3 18 NAND Flash Chip 2 Presence Register 38 Table 3 19 NAND Flash Chip 2 Status Regis...

Страница 10: ...tions 58 Table 4 7 NAND Flash Memory Configurations 58 Table 4 8 IDSEL and Interrupt Mapping for PCI Devices 59 Table 4 9 Planar PCI Device Identification 60 Table 4 10 PCI Arbitration Assignments 60 Table 4 11 LBC Timing Parameters 62 Table 4 12 Clock Assignments 62 Table 4 13 Clock Frequencies 63 Table A 1 Programmable Devices 65 Table A 2 On board Serial EEPROMs 65 Table A 3 Static VPD Contents...

Страница 11: ...rd Appendix A Programmable Configuration Data on page 65 provides additional programming information including IDSEL mapping interrupt assignments for the MPC8548E interrupt controller Flash memory two wire serial interface addressing and other device and system considerations Appendix B Related Documentation on page 79 provides a listing of related SMART Embedded Computing manuals vendor document...

Страница 12: ...e 0 and 1 bold Used to emphasize a word Screen Used for on screen output and code related elements or commands Sample of Programming used in a table 9pt Courier Bold Used to characterize user input and to separate it from system output Reference Used for references and for table and figure descriptions File Exit Notation for selecting a submenu text Notation for variables and keys text Notation fo...

Страница 13: ...result in minor or moderate injury Indicates a property damage message Indicates a hot surface that could result in moderate or serious injury Indicates an electrical situation that could result in moderate injury or death Indicates that when working in an ESD environment care should be taken to use proper ESD practices No danger encountered pay attention to important information Table 1 Conventio...

Страница 14: ...2009 Update for final release updated Feature List updated the block diagram updated System I O Memory Map System Status Register MPC8548E POR Configuration Settings MPC8548E Interrupt Controller I2C Bus Device Addressing IDSEL and Interrupt Mapping for PCI Devices PCI Arbitration Assignments LBC Timing Parameters and Variable VPD Contents added information on MRAM real time clock and Quad UART re...

Страница 15: ...d Variants Marketing Number Processor MVME4100 0171 1 3GHz MPC8548E 4GB NAND flash 2GB DDR2 Scanbe handles MVME4100 0173 1 3GHz MPC8548E 4GB NAND flash 2GB DDR2 IEEE handles Table 1 2 Features List Function Features Processor Host Controller Memory Controller One MPC8548E Integrated Processor One e500 core with integrated L2 Core frequency of 1 3 GHz One integrated four channel DMA controller One ...

Страница 16: ...rial channel Two front panel RJ 45 connectors with integrated LEDs for front I O two 10 100 1000 Ethernet channels One front panel USB Type A upright receptacle for front I O one USB 2 0 channel PMC site 1 front I O and rear P2 I O PMC site 2 front I O USB One four channel USB 2 0 controller one channel for front panel I O Ethernet Four 10 100 1000 MPC8548E Ethernet channels two front panel Ethern...

Страница 17: ...1 0 version 0 9 compliant Two five row P1 and P2 backplane connectors One Tsi148 VMEbus controller Form Factor Standard 6U VME one slot Miscellaneous One front panel RESET ABORT switch Six front panel status indicators Two 10 100 1000 Ethernet link speed and activity 4 total Board fail User S W controlled LED Planar status indicators One standard 16 pin COP header One standard 20 pin JTAG header B...

Страница 18: ... MVME4100 Single Board Computer Programmer s Reference 6806800H19D Introduction Introduction 1 3 Block Diagram The following figure is a block diagram of the MVME4100 architecture Figure 1 1 Block Diagram ...

Страница 19: ...onnectors The transition module also provides two planar connectors for one PIM with front I O The block diagram for the MVME4100 is shown in Figure 1 1 and the block diagram for the MVME7216E transition module is shown in the Transition Module section of the MVME4100 Single Board Computer Installation and Use manual 1 5 Programming Model The MVME4100 programming model is based on the MPC8548E loc...

Страница 20: ...20 MVME4100 Single Board Computer Programmer s Reference 6806800H19D Introduction Introduction ...

Страница 21: ... view of the processor This table reflects the address map implemented by the board level firmware at release time Table 2 1 Default Processor Address Map Processor Address Size Definition Notes Start End 0000 0000 FF6F FFFF 4087 M Not mapped FF70 0000 FF7F FFFF 1 M MPC8548E CCSR Registers FF80 0000 FFFF FFFF 8 M Flash 1 1 The e500 core fetches the first instruction from FFFF FFFC following a rese...

Страница 22: ... F0FF FFFF 8 MB PCI 1 I O Space F100 0000 F10F FFFF 1 MB MPC8548E CCSR F110 0000 F1FF FFFF 15 MB Not used F200 0000 F200 FFFF 64 KB Status Control Registers F201 0000 F201 FFFF 64 KB UARTs F202 0000 F202 FFFF 64 KB Timers F203 0000 F203 FFFF 64 KB NAND Flash F204 0000 F23F FFFF 3 9 MB Not used F240 0000 F247 FFFF 512 KB MRAM F248 0000 F7FF FFFF 91 5 MB Not used F800 0000 FFFF FFFF 128 MB NOR Flash...

Страница 23: ...ble 3 1 System I O Memory Map Address Definition LBC Bank Chip Select Notes F200 0000 System Status Register 4 3 F200 0001 System Control Register 4 3 F200 0002 Status Indicator Register 4 3 F200 0003 NOR Flash Control Status Register 4 3 F200 0004 Interrupt Register 1 4 3 F200 0005 Interrupt Register 2 4 3 F200 0006 Presence Detect Register 4 3 F200 0008 PCI Bus Status Register 1 4 3 F200 0009 PC...

Страница 24: ...us Register 4 3 F200 001E Reserved 4 1 F200 001F Reserved 4 1 F200 0020 Watch Dog Timer Load 4 3 F200 0021 Reserved 4 1 F200 0022 Reserved 4 1 F200 0023 Reserved 4 1 F200 0024 Watchdog Control 4 3 F200 0025 Watchdog Resolution 4 F200 0026 F200 0027 Watchdog Count 4 F200 0028 Reserved 32 bits 4 1 F200 002C Reserved 32 bits 4 1 F200 0030 PLD Revision 4 3 F200 0031 Reserved 4 1 F200 0032 Reserved 4 1...

Страница 25: ...er 6 2 F202 0014 External PLD Tick Timer 1 Compare Register 6 2 F202 0018 External PLD Tick Timer 1 Counter Register 6 2 F202 001C Reserved 6 2 F202 0020 External PLD Tick Timer 2 Control Register 6 2 F202 0024 External PLD Tick Timer 2 Compare Register 6 2 F202 0028 External PLD Tick Timer 2 Counter Register 6 2 F202 002C Reserved 6 2 F202 0030 External PLD Tick Timer 3 Control Register 6 2 F202 ...

Страница 26: ...0044 External PLD Tick Timer 4 Compare Register 6 2 F202 0048 External PLD Tick Timer 4 Counter Register 6 2 F202 004C F2FF FFFF Reserved 6 1 F203 0000 NAND Chip 1 Data Register 2 3 F203 0001 F203 0FFF Reserved 2 1 F203 1000 NAND Chip 2 Data Register 2 3 F203 1001 F203 FFFF Reserved 2 1 Table 3 1 System I O Memory Map continued Address Definition LBC Bank Chip Select Notes Table 3 2 System Status ...

Страница 27: ...t reflects the current state of the PCI 66 switch A cleared condition indicates the switch is off A set condition indicates the switch is on MASTER WP MASTER WP This bit reflects the current state of the MASTER WP switch A cleared condition indicates the switch is off A set condition indicates the switch is on When this switch is on the NOR FLASH NAND FLASH MRAM and I2C EEPROMs are write protected...

Страница 28: ... when the board reset has been completed These bits are always cleared during a read RSVD Reserved for future implementation Table 3 4 Status Indicator Register REG Status Indicator Register 0xF200 0002 BIT 7 6 5 4 3 2 1 0 Field RSVD RSVD RSVD RSVD USR3 USR2 USR1 Y USR1 R OPER R R R R R W R W R W R W RESET 0 0 0 0 0 0 0 1 USR1R User LED 1 RED This bit is used to control the USR1 bi color LED locat...

Страница 29: ...ot block A is selected and mapped to the highest address A set condition indicates that boot block B is selected and mapped to the highest address see Figure 3 1 F_WP_HW Hardware Flash Bank Write Protect switch status This bit reflects the current state of the FLASH BANK WP switch A set condition indicates that the NOR Flash bank is write protected A cleared condition indicates that the flash bank...

Страница 30: ... 0xF200 0004 BIT 7 6 5 4 3 2 1 0 Field RSVD RSVD RSVD RSVD PHY4 PHY3 PHY2 PHY1 OPER R RESET 0 0 0 0 0 0 0 0 PHY1 TSEC1 PHY Interrupt If cleared the TSEC1 interrupt is not asserted If set the TSEC1 interrupt is asserted PHY2 TSEC2 PHY Interrupt If cleared the TSEC2 interrupt is not asserted If set the TSEC2 interrupt is asserted PHY3 TSEC3 PHY Interrupt If cleared the TSEC3 interrupt is not asserte...

Страница 31: ...h is not depressed while a set condition indicates that the abort switch is asserted TEMP Status TEMP Status If cleared the Temperature sensor output is not asserted If set the Temperature sensor output is asserted RTC Status RTC Status If cleared the RTC output is not asserted If set the RTC output is asserted ABORT Mask ABORT Mask This bit is used to mask the abort switch output If this bit is c...

Страница 32: ... is installed PMC2P PMC Module 2 Present If cleared there is no PMC module installed in site 2 If set the PMC module is installed XEP XMCspan Present If cleared there is no XMCspan module installed If set the XMCspan module is installed ERDY1 EREADY1 Indicates that the PrPMC module installed in PMC site 1 is ready for enumeration when set If cleared the PrPMC module is not ready for enumeration If...

Страница 33: ...REG PCI Bus 2 Status Register 0xF200 0009 BIT 7 6 5 4 3 2 1 0 Field 3 3V_VIO 5 0V_VIO RSVD RSVD PCI_2_64B PCIX_2 PCI_2_SPD OPER R R R R R R R R RESET X X X 0 1 X X X PCI_2_SPD PCI Bus 2 Speed Indicates the frequency of PCI bus 2 00 33 MHz 01 66 MHz 10 100 MHz 11 133 MHz PCIX_2 PCI X Bus 2 A set condition indicates that bus 2 is operating in PCI X mode Cleared indicates PCI mode PCI_2_64B PCI Bus 2...

Страница 34: ...SET 0 0 0 0 0 0 0 0 PCI_3_SPD PCI Bus 3 Speed Indicates the frequency of PCI bus 3 00 33 MHz 01 66 MHz 10 100 MHz 11 133 MHz PCIX_3 PCI X Bus 3 A set condition indicates that bus 3 is operating in PCI X mode Cleared indicates PCI mode PCI_3_64B PCI Bus 3 64 bit A set condition indicates that bus 3 is enabled to operate in 64 bit mode Cleared indicates 32 bit mode RSVD Reserved for future implement...

Страница 35: ...cessed RSVD Reserved for future implementation Table 3 13 NAND Flash Chip 1 Select Register REG NAND Flash Chip 1 Select Register 0xF200 0011 BIT 7 6 5 4 3 2 1 0 Field CE1 CE2 CE3 CE4 RSVD RSVD RSVD RSVD OPER R W R RESET 0 0 0 0 0 0 0 0 CE4 Chip Enable 4 If cleared CE4 is not asserted when the device is accessed If set CE4 is asserted when the device is accessed CE3 Chip Enable 3 If cleared CE3 is...

Страница 36: ...VD RSVD OPER R RESET X 0 0 0 0 0 0 0 C1P Chip 1 Present If cleared chip 1 is not installed on the board If set chip 1 is installed on the board RSVD Reserved for future implementation Table 3 15 NAND Flash Chip 1 Status Register REG NAND Flash Chip 1 Status Register 0xF200 0015 BIT 7 6 5 4 3 2 1 0 Field RB1 RB2 RB3 RB4 RSVD RSVD RSVD RSVD OPER R RESET 1 1 1 1 0 0 0 0 RB4 Ready Busy 4 If cleared De...

Страница 37: ...RSVD OPER R W R RESET 0 0 1 0 0 0 0 0 WP Write Protect If cleared WP is not asserted when the device is accessed If set WP is asserted when the device is accessed ALE Address Latch Enable If cleared ALE is not asserted when the device is accessed If set ALE is asserted when the device is accessed CLE Command Latch Enable If cleared CLE is not asserted when the device is accessed If set CLE is asse...

Страница 38: ...the device is accessed CE2 Chip Enable 2 If cleared CE2 is not asserted when the device is accessed If set CE2 is asserted when the device is accessed CE1 Chip Enable 1 If cleared CE1 is not asserted when the device is accessed If set CE1 is asserted when the device is accessed RSVD Reserved for future implementation Table 3 18 NAND Flash Chip 2 Presence Register REG NAND Flash Chip 2 Presence Reg...

Страница 39: ...SVD RSVD RSVD RSVD OPER R RESET 1 1 1 1 0 0 0 0 RB4 Ready Busy 4 If cleared Device 4 is busy If set device 4 is ready RB3 Ready Busy 3 If cleared Device 3 is busy If set device 3 is ready RB2 Ready Busy 2 If cleared Device 2 is busy If set device 2 is ready RB1 Ready Busy 1 If cleared Device 1 is busy If set device 1 is ready RSVD Reserved for future implementation Table 3 20 Watch Dog Timer Load ...

Страница 40: ...SVD RSVD OPER R W R RESET 0 0 0 0 0 0 0 0 SYSRST System Reset If cleared a board level reset is generated when a time out occurs If set a VMEbus SYSRST is generated when a time out occurs If MVME4100 is SYSCON then a local reset will also result in a VMEbus SYSRST EN Enable If cleared the watch dog timer is disabled If set the watch dog timer is enabled RSVD Reserved for future implementation Tabl...

Страница 41: ...Register REG Watch Dog Timer Counter Register 0xF200 0026 BIT 15 0 Field Count OPER R W RESET 03FF COUNT Count These bits define the watch dog timer count value When the watch dog counter is enabled or there is a write to the load register the watch dog counter is set to the count value When enabled the watch dog counter will decrement at a rate defined by the resolution register The counter will ...

Страница 42: ...VME4100 PLD provides a 32 bit register which contains the build date code of the timers registers PLD Table 3 24 PLD Revision Register REG PLD Revision Register 0xF200 0030 BIT 7 6 5 4 3 2 1 0 Field PLD_REV OPER R RESET 01 PLD_RE V 8 bit field containing the current timer register PLD revision The revision number starts with 01 Table 3 25 PLD Date Code Register REG Date Code Register 1 0xF200 0034...

Страница 43: ...second 32 bit test register that reads back the complement of the data in Test Register 1 Table 3 26 Test Register 1 REG Test Register 1 0xF200 0038 BIT 31 0 Field TEST1 OPER R W RESET 0000 TEST1 General purpose 32 bit R W field Table 3 27 Test Register 2 REG Test Register 2 0xF200 003C BIT 31 0 Field TEST2 OPER R W RESET FFFF TEST2 A read from this address will return the complement of the data p...

Страница 44: ...s 3 1 25 1 Prescaler Register The Prescaler Adjust value is determined by this formula Prescaler Adjust 256 CLKIN CLKOUT Where CLKIN is the input clock source in MHz and CLKOUT is the desired output clock reference in MHz The prescaler provides the clock required by each of the four timers The tick timers require a 1 MHz clock input The input clock to the prescaler is 25 MHz The default value is s...

Страница 45: ...5 4 3 2 1 0 Field R S V D R S V D I N T S C I N T E N I N T OVF R S V D C O V F C O C E N C OPER R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 ENC Enable counter When the bit is set the counter increments When the bit is cleared the counter does not increment COC Clear Counter on Compare When the bit is set the counter is reset to 0 when it compares with the compare register When the bit is cleared the coun...

Страница 46: ...aphical address of the MVME4100 This register reflects the inverted states of the geographical address pins at the 5 row 160 pin P1 connector Applications not using the 5 row backplane can use the planar switch described in the MVME4100 Installation and Use manual to assign a geographical address Table 3 30 Tick Timer Compare Registers REG Tick Timer 1 Compare Register 0xF202 0014 32 bits Tick Tim...

Страница 47: ...ameters on page 62 Other Software Considerations on page 61 Clock Distribution on page 62 4 2 MPC8548E Reset Configuration The MVME4100 supports the power on reset POR pin sampling method for processor reset configuration The states of the various configuration pins on the processor are sampled when reset is deasserted to determine the desired operating modes Combinations of pull up and pull down ...

Страница 48: ...I1_CLK 0 PCI1_CLK is used as the PCI1 clock 1 SYSCLK is used as the PCI clock PCI1_GNT1_L Resistor 0 PCI1 interface I O impedance 0 25 Ohm drivers 1 42 Ohm drivers PCI1_GNT2_L Fixed 1 PCI arbiter configuration 0 Disable on chip PCI PCI X arbiter 1 Enable on chip PCI PCI X arbiter PCI1_GNT3_L Fixed 1 PCI debug configuration 0 PCI debug enabled 1 PCI operates in normal mode PCI1_GNT4_L PLD 0 PCI PCI...

Страница 49: ...ced mode 10 TSEC1 controller uses GMII protocol RGMII if TSEC1 configured in reduced mode 11 TSEC1 controller uses TBI protocol RTBI if TSEC1 configured in reduced mode TSEC1_TCD 6 4 Fixed 111 Boot ROM location 000 PCI1 PCI X 001 DRR SDRAM 010 PCI2 011 Serial Rapid IO 100 PCI Express 101 Local bus GPCM 8 bit ROM 110 Local bus GPCM 16 bit ROM 111 Local bus GPCM 32 bit ROM Table 4 1 MPC8548E POR Con...

Страница 50: ...ixed 10 TSEC2 protocol configuration 00 TSEC2 controller uses 16 bit FIFO mode 8 bit FIFO mode if TSEC2 configured in reduced mode 01 TSEC2 controller uses MII protocol RMII if TSEC2 configured in reduced mode 10 TSEC2 controller uses GMII protocol RGMII if TSEC2 configured in reduced mode 11 TSEC2 controller uses TBI protocol RTBI if TSEC2 configured in reduced mode TSEC2_TXD 1 TSEC2_RX_ER Fixed ...

Страница 51: ... Fixed 0 TSEC 3 and 4 configuration width 0 TSEC 3 and 4 in reduced mode RTBI or RGMII 1 TSEC 3 and 4 in standard mode TBI or GMII TSEC4_TXD 0 TSEC4_TXD 7 Fixed 10 TSEC4 protocol configuration 00 Reserved 01 TSEC4 controller uses RMII protocol 10 TSEC3 controller uses RGMII protocol 11 TSEC3 controller uses RTBI protocol TSEC4_TXD 2 Fixed 1 SerDes enable 0 SerDes interface is disabled 1 SerDes int...

Страница 52: ...PCI above 33 MHz PCI X above 66 MHz LWE 1 3 _L PLD 111 Host agent configuration 000 Agent of RapidIO and PCI Express host for PCI1 PCI X 001 Agent of a RapidIO host PCI Express and PCI1 PCI x 010 Endpoint PCI Express host RapidIO and PCI PCI X 011 Reserved 100 Agent PCI1 PCI X and RapidIO root complex PCI Express 110 Agent PCI1 PCI X host RapidIO root complex PCI Express 111 Host processor root co...

Страница 53: ...mal I2C address mode 10 Boot sequencer enabled with extended I2C address mode 11 Boot sequencer disabled MSRCID0 Fixed 1 Memory debug configuration 0 Debug info from the LBC is driven on MSRCID and MDVAL pins 1 Debug info from the DDR SDRAM controller is driven on MSRCID and MDVAL pins MSRCID1 Fixed 1 DDR debug configuration 0 Debug info on ECC pins instead of normal ECC 1 ECC pins function in nor...

Страница 54: ... External timers are implemented in a PLD 2 External UARTs are implemented using a QUART Refer to the MPC8548E Reference Manual listed in Appendix B Related Documentation for additional details regarding the operation of the MPC8548E PIC Table 4 2 MPC8548E Interrupt Controller Interrupt Edge Level Polarity Interrupt Source Notes 0 Level Low Tsi148 INTA 1 Level Low Tsi148 INTB 2 Level Low Tsi148 IN...

Страница 55: ...ntrol Status registers are byte read and write capable 3 32 bit timer registers are byte readable but must be written as 32 bits 4 MRAM is byte read and write capable Table 4 3 LBC Chip Select Assignments LBC Bank Chip Select Local Bus Function Size Data Bus Width Notes 0 Boot flash bank 128 MB 32 bits 1 1 Boot flash bank 128 MB 32 bits 1 2 NAND flash bank 64 KB 8 bits 3 MRAM 512 KB 16 bits 4 4 Co...

Страница 56: ... recommended address setting for the MVME4100 is AA 4 6 User Configuration EEPROM The board provides two 64 KB dual address serial EEPROMs for a total of 128 KB user configuration storage These EEPROMs are hardwired to have device IDs as shown in Table 4 4 on page 56 and each device ID will not be used for any other function Refer to the EEPROM Data Sheet listed in Appendix B Related Documentation...

Страница 57: ...figuration information specific to the MVME4100 RTM Typical information that may be present in the EEPROM may include manufacturer board revision build version date of assembly options present etc The RTM VPD EEPROM device ID is user selectable with the recommended value for MVME4100 as shown in Table 4 4 on page 56 Refer to the EEPROM Data Sheet listed in Appendix B Related Documentation for addi...

Страница 58: ...n is controlled by the state of the software flash write protect bits It is only disabled by clearing this bit in the NOR Flash Control Status register refer to section NOR Flash Control Status Register on page 29 Note that the F_WP_HW bit reflects the state of the switch and is only software readable whereas the F_WP_SW bit supports both read and write operations Also included is one bank of NAND...

Страница 59: ...heet for details on generating configuration cycles on each of the PCI busses Refer to the MPC8548E reference manual for additional details about the MPC8548E PIC operation Table 4 8 IDSEL and Interrupt Mapping for PCI Devices PCI Bus Device Number Field AD Line for IDSEL PCI Device or Slot Device Slot INT to MPC8548E IRQ INTA INTB INTC INTD PCI1 8548E 0b0_0000 internal MPC8548E 0b0_0001 17 Tsi148...

Страница 60: ... Table 4 9 Planar PCI Device Identification Function Device Vendor ID Device ID System Controller MPC8548E 0x1957 0x0012 PCI X to PCI X Bridge PCI6520 0x10B5 0x6520 VME Controller TSi148 0x10E3 0x0148 USB Controller µPD720101 0x1033 0x0035 Table 4 10 PCI Arbitration Assignments PCI Bus Arbitration Assignment PCI Master s 1 8548E REQ GNT 0 PCI6520 PCI X to PCI X Bridge 1 8548E REQ GNT 1 PCI6520 PCI...

Страница 61: ...ware must first ensure that the MRAM s write protection mechanisms have been modified to allow write access to the MRAM 4 12 2 Real Time Clock The MVME4100 provides a battery backed up DS1375 RTC Real TIme Clock chip The RTC chip provides time keeping and alarm interrupts The RTC chip is an I2 C device and is accessed via the I2 C bus at address 0xD0 4 12 3 Quad UART The MVME4100 console RS 232 po...

Страница 62: ...ver The PCI PCI X bus clocks are generated using a MPC9855 clock generator Additional clocks required by individual devices are generated near the devices using individual oscillators The following table lists the clocks required on the MVME4100 along with their frequency and source Table 4 11 LBC Timing Parameters 0 NOR Flash 1 NOR Flash 2 NAND Flash 3 MRAM 4 CSR 5 UART 6 Timers LBCTLD 0 0 0 0 0 ...

Страница 63: ... CLK_PCI2 33 66 100 MPC9855 1 3 3 V Tsi148 CLK_PCI3 66 100 MPC9855 1 3 3 V USB CLK_PCI4 33 MPC9855 1 3 3 V BCM5482S CLK2_25MHZ 25 Oscillator Buffer 1 2 5 V BCM5482S CLK3_25MHZ 25 Oscillator Buffer 1 2 5 V Control andTimers PLD CLK1_25MHZ CLK_LBP 25 MPX CLK 8 Oscillator Buffer MPC8548E 1 1 3 3 V 3 3 V QUART CLK_1 8M 1 8432 Oscillator 1 3 3 V USB CLK_48MHZ 48 Oscillator 1 3 3 V RTC CLK_32K 32 768 KH...

Страница 64: ...omputer Programmer s Reference 6806800H19D Programming Details Programming Details 4 13 3 Local Bus Controller Clock Divisor The Local Bus Controller LBC clock output is connected to the PLD but is not used by the internal logic ...

Страница 65: ...figuration data are Vital Product Data VPD pertaining to all board functions only one on the board Vital Product Data VPD for the RTM Serial Presence Detect SPD pertaining to SDRAM characteristics one per bank EEPROMs for configuration data storage The following table lists the on board and transition module serial EEPROMs Table A 1 Programmable Devices Location Raw Part Manufacturer Part Specific...

Страница 66: ...Factory Assembly Number 0106855E03x 0106855E04x Serial number of the specific MVME4100 Processor family number xxx Hardware clock frequencies internal external fixed PCI bus Component configuration information connectors Ethernet addresses flash bank ID L2 cache ID Security information VPD type version and revision data 32 bit CRC protection A 4 How to Read and Modify VPD Information vpdDisplay ma...

Страница 67: ...diagnostic tests and firmware commands may hang or fail in unexpected ways A 8 How to Fix Wrong VPD Problems If you suspect that your board has problems as a result of wrong VPD information select SAFE mode by setting S1 1 ON and reboot the MVME4100 At this point the firmware will ignore all SROM contents Use SROM or the IBM command to change the VPD to the correct parameters A 9 Vital Product Dat...

Страница 68: ...nsigned int crcValue unsigned int crcValueFlipped unsigned char dataByte unsigned int index dataBitValue msbDataBitValue crcValue 0xffffffff for index 0 index vpdSromSize index dataByte pVpdBuffer for dataBitValue 0 dataBitValue 8 dataBitValue msbDataBitValue crcValue 31 1 crcValue 1 if msbDataBitValue dataByte 1 crcValue 0x04c11db6 crcValue 1 dataByte 1 crcValueFlipped 0 for index 0 index 32 inde...

Страница 69: ... is noted between either or these tables and your board please contact your support representative to determine which is accurate Table A 3 Static VPD Contents Offset HEX Data HEX Field Type Description 00 45 ASCII Eye Catcher SMART EC Note Lowest CRC byte for the calculation of CRC 01 4D 02 45 03 52 04 53 05 4F 06 4E 07 20 08 02 BINARY Size of VPD area in bytes The size is viewed as logical it is...

Страница 70: ...Refer to Notes 1 and 2 11 14 BINARY of bytes 12 xx ASCII Product Identifier Refer to Table A 4 13 xx 14 xx 15 xx 16 xx 17 xx 18 xx 19 xx 1A xx 1B xx 1C xx 1D xx 1E xx 1F xx 20 xx 21 xx 22 xx 23 xx 24 xx 25 xx 26 02 BINARY Factory Assembly Number Refer to Notes 1 and 2 27 0D BINARY of bytes Table A 3 Static VPD Contents continued Offset HEX Data HEX Field Type Description ...

Страница 71: ...x 31 xx 32 xx 33 xx 34 xx 35 03 BINARY Serial number to be filled in Refer to Notes 2 and 3 36 07 BINARY of bytes 37 xx ASCII Most significant serial number character 38 xx 39 xx 3A xx 3B xx 3C xx 3D xx Least significant serial number character 3E 06 BINARY External Processor Clock Frequency Packet 3F 05 BINARY of bytes Table A 3 Static VPD Contents continued Offset HEX Data HEX Field Type Descrip...

Страница 72: ...s Packet 46 07 BINARY of bytes 47 xx BINARY Six bytes containing the lowest Ethernet address 48 xx 49 xx 4A xx 4B xx 4C xx 4D 00 BINARY Ethernet Controller 0 4E 08 BINARY Ethernet MAC Address Packet 4F 07 BINARY of bytes 50 xx BINARY Six bytes containing the next Ethernet address 51 xx 52 xx 53 xx 54 xx 55 xx 56 01 BINARY Ethernet Controller 1 57 08 BINARY Ethernet MAC Address Packet 58 07 BINARY ...

Страница 73: ...ntroller 2 60 08 BINARY Ethernet MAC Address Packet 61 07 BINARY of bytes 62 xx BINARY Six bytes containing the highest Ethernet address 63 xx 64 xx 65 xx 66 xx 67 xx 68 03 BINARY Ethernet Controller 3 69 09 BINARY Processor Identifier Packet 6A 05 BINARY of bytes 6B xx ASCII Processor type Refer to Table A 4 6C xx 6D xx 6E xx 6F xx Table A 3 Static VPD Contents continued Offset HEX Data HEX Field...

Страница 74: ...x BINARY CRC to be filled in 73 xx 74 xx 75 xx 76 0B BINARY Bank 1 Flash Memory Configuration Packet 77 0C BINARY of bytes 78 00 BINARY Vendor Identifier 79 01 7A 7E BINARY Device Identifier 7B 23 7C 10 BINARY Single device width in bits 7D 02 BINARY Number of devices or sockets present 7E 01 BINARY Number of interleave columns 7F 20 BINARY Column width in bits 80 20 BINARY Minimum write erase dat...

Страница 75: ...que The board s serial number is obtained from the onboard serial number label 84 0B BINARY Bank 2 Flash Memory Configuration Packet 85 0C BINARY of bytes 86 00 BINARY Vendor Identifier 87 EC 88 D5 BINARY Device Identifier 89 51 8A 08 BINARY Single device width in bits 8B 01 BINARY Number of devices or sockets present 8C 01 BINARY Number of interleave columns 8D 08 BINARY Column width in bits 8E 0...

Страница 76: ...ddress 0x32 represents the assembly revision letter A 41 B 42 etc Table A 4 Variable VPD Contents Offset Hex MVME4100 0171 MVME4100 0173 0106855E03x 0106855E04x 12 4D 4D 13 56 56 14 4D 4D 15 45 45 16 34 34 17 31 31 18 30 30 19 30 30 1A 2D 2D 1B 31 31 1C 37 37 1D 31 33 1E 20 20 1F 20 20 20 20 20 21 20 20 22 20 20 23 20 20 24 20 20 25 20 20 28 30 30 29 31 31 ...

Страница 77: ...s Reference 6806800H19D 77 2A 30 30 2B 36 36 2C 38 38 2D 35 35 2E 35 35 2F 45 45 30 30 30 31 33 34 32 XX XX 33 00 00 34 00 00 40 03 03 41 F9 F9 42 40 40 43 AA AA 91 0F 0F Table A 4 Variable VPD Contents continued Offset Hex MVME4100 0171 MVME4100 0173 0106855E03x 0106855E04x ...

Страница 78: ...78 MVME4100 Single Board Computer Programmer s Reference 6806800H19D Programmable Configuration Data Programmable Configuration Data ...

Страница 79: ... that while these sources have been verified the information is subject to change without notice Table B 1 SMART EC Publications Document Title Publication Number MVME4100 Data Sheet MVME4100 DS MVME4100 Single Board Computer Installation and Use 6806800H18 MOTLoad Firmware Package User s Manual 6806800C24 Table B 2 Manufacturer s Publications Document Title and Source Publication Number Spansion ...

Страница 80: ... Transceiver and Two 1 bit Bus Transceivers with Split LVTTL Port Feedback Path and 3 state Outputs SCES357E Revised March 2004 Exar ST16C554 554D ST68C554 Quad UART with 16 Byte FIFO s Version 4 0 1 June 2006 Maxim Integrated Products DS1375 Serial Real Time Clock REV 121203 MAX3221E MAX3223E MAX3243E 15kV ESD Protected 1µA 3 0V to 5 5V 250kbps RS 232 Transceivers with Auto Shutdown 19 1283 Rev 5...

Страница 81: ...100 1000BASE T Gigabit Ethernet Transceiver 5482S DS06 R 2 15 07 PLX Technology PCI6520 PCI X to PCI X Bridge Databook Version 2 0 Table B 2 Manufacturer s Publications continued Document Title and Source Publication Number Table B 3 Related Specifications Organization and Standard Document Title VITA Standards Organization VME64 ANSI VITA 1 1994 VME64 Extensions ANSI VITA 1 1 1997 2eSST Source Sy...

Страница 82: ...al Addendum to the PCI Local Bus Specification Revision 2 0a PCI X EM 2 0a August 22 2003 PCI X Protocol Addendum to the PCI Local Bus Specification Revision 2 0a PCI X PT 2 0a July 22 2003 Institute for Electrical and Electronics Engineers Inc IEEE Standard for a Common Mezzanine Card Family CMC Family IEEE Std 1386 2001 IEEE Standard Physical and Environmental Layer for PCI Mezzanine Cards PMC I...

Страница 83: ...1 ...

Страница 84: ...registered trademark of SMART Modular Technologies Inc and SMART Embedded Computing and the SMART Embedded Computing logo are trademarks of SMART Modular Technologies Inc All other names and logos referred to are trade names trademarks or registered trademarks of their respective owners ...

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