SMART Embedded Computing MVME2502, Инструкция по установке и эксплуатации

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Programming Model
MVME2502 Installation and Use (6806800R96L) 135
7.5 Ethernet PHY Address
The assigned Ethernet PHY on the MII management bus is shown in the following table.
7.6 Other Software Considerations
The following sections provide programming information in relation to various board
components:
7.6.1 MRAM
The MVME2502 provides 512K bytes of fast, non-volatile storage in the form of
Magnetoresistive Random Access Memory (MRAM). The MRAM is directly accessible by
software using processor load and store instructions similar to the DRAM. The difference
is that the MRAM retains its contents even if the board is power cycled. The MRAM is
accessed through the LBC.
7.6.2 Real Time Clock
The MVME2502 provides a battery backup DS1375 Real Time Clock (RTC) chip. The RTC
chip provides time keeping and alarm interrupts. It is an I
2
C device and is accessed through
the I
2
C bus address at 0x68.
7.6.3 Quad UART
The MVME2502 console RS-232 port is driven by the UART built into the P2020 QorIQ
chip. Additionally, the MVME2502 has a Quad UART chip which provides four 16550
compatible UARTs. These additional UARTs are internally accessed through the LBC bus.
The Quad UART chip clock input (which is internally divided to generate the baud rate) is
1.8432MHz. The four UARTs physically connect to RS-232 DB9 serial ports through the
RTM.
Table 7-4 PHY Types and MII Management Bus Address
Ethernet
Port
Function / Location PHY Types
PHY MIIM
Address
TSEC1
Gigabit Ethernet port routed to front panel or back
panel, set by GBE_MUX_SEL in S2.
BCM54616 1
TSEC2 Gigabit Ethernet port routed to front panel BCM54616 2
TSEC3 Gigabit Ethernet port routed to back panel BCM54616 7