PCI302 - Operation & Maintenance Instructions Manual
4
CPU (Central Processing Unit)
A 32-bit super-scalar RISC processor that handles all communication and control tasks performed
by the PCI302.
DP (Dual Port RAM)
16-bit data memory shared with the PC through the PC bus. Both PCI302 and PC CPUs have
simultaneous access to this memory, providing an efficient communication path between them.
Control Logic
Internal control logic to handle the CPU access to all devices (RAM, NVRAM, FLASH, TIMERs,
MODEMs), and the DP arbitration mechanism.
PC Bus (Computer Expansion Bus)
A PCI bus (specification v2.1) (*), 16-bit ISA or 32-bit EISA bus, on which the PCI302 cards are
plugged. It provides power and PC access to the card.
Local Bus (High Speed Wide Bus)
A 32-bit internal bus that interconnects the CPU to fast devices (RAM, NVRAM, FLASH and DP).
Peripheral Bus
8-bit peripheral bus used by the CPU to connect to slow devices (TIMERs and MODEMs).
Timer
0 - 5
8/16-bit 3-channel universal timers, used by the PSM-Real Time Kernel as a time base for task
switching and the Fieldbus communication timing.
Modem
0 - 3
(Fieldbus Communications Controller)
The Smar Fieldbus chips that serialize the data communication at a 31.25Kbps baud rate. It is ISA-
SP50 Fieldbus Physical Layer Specification compliant.
MAU
0 - 3
(Fieldbus Medium Attachment Unit)
A signal conditioning and isolation circuit that adapts the digital signal (0/5V) from the modem to the
Fieldbus lines, according to the ISA-SP50.02-1992 Fieldbus Physical Layer Specification. The
PCI302 MAU is passive, that is, not powered by the bus.
NVRAM (
Non-Volatile Random Access Memory
)
The 32-bit data memory is where the PCI302 data structures and objects are stored.
FLASH (Flash Memory)
32-bit code memory, where the PCI302 program is stored.
