Smacq Technologies PCI-1255, Руководство пользователя

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24
Chapter 5 Register Detail
If you do not want to use the file "pci-1255.dll", but develop applications by working directly
with I/O port read and write operations through PCI interface, please carefully read the following
register description list.
Corresponding address
（
Base a Decimal offset
address
）
Operation Notes
Base address
＋
0 Write
BIT4-BIT0
：
Set current AD channel number
（
0
～
31
）
When in auto-switching channel mode, set ending
channel number.
BIT5
：
0 singled-ended
；
1 double-ended
Base address
＋
0 Read
When in software start mode, read AD conversion result
（
lower 12 digits are valid
）
Base address
＋
4 Write
Clear hardware FIFO
Set current channel number as 0 in auto-switching
channel mode.
Base address
＋
4 Read
When in software start mode
，
start AD conversion once.
When in external trigger (timing) start mode, read data
from FIFO.
Base address
＋
8 Write Set 16 digits switch output status (Bit0
～
Bit15)
Base address
＋
8
Read
Read 16 digits switch input status (Bit0
～
Bit15)
Base address
＋
12 Read/Write Return/Set counter 0 value
Base address
＋
16
Read/Write Return/Set counter 1 value
Base address
＋
20
Read/Write Return/Set counter 2 value
Base address
＋
24 Write Set 82C54 control word
Base address
＋
32 Read/Write
Onboard register setting
BIT0
：
1
，
AD acquiring
；
0
，
AD acquisition done
BIT1
：
1
，
FIFO not full
；
0
，
FIFO full
BIT2
：
1
，
FIFO not half full
；
0
，
FIFO half full
BIT3
：
1
，
FIFO not empty
；
0
，
FIFO empty
BIT4
：
1
，
External trigger
（
timing
）
start AD
；
0
，
software
start AD
BIT5
：
1
，
FIFO half full interrupt is valid
；
0
，
external trigger
interrupt is valid
BIT6
：
1
，
auto-switching channel
；
0
，
fixed channel
Base address
＋
36 Read Clear external trigger interrupt