Sintrones VBOX-3600, Руководство пользователя

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5.0 System Resource
User’s Manual Page 5-7
Watchdog Timer Configuration Register 1 ‐ base address +05h
Bit Name R/W Default Description
7 Reserved R 0 Reserved
6 WDTMOUT_STS R/W 0 If watchdog timeout event occurs, this bit will be set to
1. Write a 1 to this bit will clear it to 0.
5 WD_EN R/W 0 If this bit is set to 1, the counting of watchdog time is
enabled.
4 WD_PULSE R/W 0 Select output mode (0:level, 1:pulse) of RSTOUT# by
setting this bit.
3 WD_UNIT R/W 0 Select time unit (0:1sec, 1:60sec) of watchdog timer by
setting this bit.
2 WD_HACTIVE R/W 0 Select output polarity of RETOUT# (1:high active, 0:low
active) by setting the bit.
1 ‐ 0 WD_PSWIDTH R/W 0 Select output pulse width of RSTOUT#
0:1 ms 1:25 ms
2:125 ms 3:5 sec
Watchdog Timer Configuration Register 2 ‐ base address +06h
Bit Name R/W Default Description
7 ‐ 0 WD_TIME R/W 0 Time of watchdog timer
Watchdog PME Control Register ‐ base address + 0Ah
Bit Name R/W Default Description
7 WDT_PME R ‐‐ The PME Status
This bit will set when WDT_PME_EN is set and the
watchdog timer is 1 unit before time out (of time out)
6 WDT_PME_EN R/W 0 0 : Disable Watchdog PME.
1 : Enable Watchdog PME
5 ‐ 1 Reserved ‐‐ ‐‐ Reserved
0 WDOUT_EN R/W 0 0 : disable Watchdog time out output via WDTRST#
1 : enable Watchdog time out output via WDTRST#