SH69P55A/K55A
25
(1) Timer Mode
In this mode, Timer2 is performed using the internal system clock. The contents of the Timer2 load register ($384 - $387) are
loaded into the up-counter while the highest nibble ($387) has been written. The up-counter will start counting if the Timer2
control register ($27) T2GO (bit3) is set to 1. The Timer2 interrupt will issue when the up-counter overflows from $FFFF to
$0000 if the Interrupt enable register ($00) IET2 (bit1) is set to 1.
After the Timer2 control register ($27) T2GO (bit3) has been set to 1, writing the Timer2 load register ($384 - $387) can not
affect the up-counter operating anymore. Only when the Timer2 control register ($27) T2GO (bit3) has been cleared to 0, the
contents of the Timer2 load register ($384 - $387) will be loaded into the up-counter while the highest nibble ($387) is written.
Timer2 Pre-scaler Register: $15
Address
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Remarks
$15 T2E
T2SC.2
T2SC.1
T2SC.0
R/W
Bit2-0: Timer2 pre-scaler register
Bit3: T2 external signal edge select register
X 0 0 0
R/W
Timer clock source: f
SYS
/2
11
X 0 0 1
R/W
Timer clock source: f
SYS
/2
9
X 0 1 0
R/W
Timer clock source: f
SYS
/2
7
X 0 1 1
R/W
Timer clock source: f
SYS
/2
5
X 1 0 0
R/W
Timer clock source: f
SYS
/2
3
X 1 0 1
R/W
Timer clock source: f
SYS
/2
2
X 1 1 0
R/W
Timer clock source: f
SYS
/2
1
X 1 1 1
R/W
Timer clock source: f
SYS
/2
0
0
X
X
X
R/W
Increment on high-to-low transition T2 input
1
X
X
X
R/W
Increment on low-to-high transition T2 input
(2) External Event Counter Mode
In this mode, Timer2 is performed using the external clock via T2 pin (shared with PORTG3). Either the rising or falling edge
can be selected with the external trigger controlled by the Timer2 pre-scaler register ($15) T2E (bit3). The contents of the
Timer2 load register ($384 - $387) are loaded into the up-counter while the highest nibble ($387) has been written. The
up-counter will start counting if the Timer2 control register ($27) T2GO (bit3) is set to 1. The Timer2 interrupt will issue when
the up-counter overflows from $FFFF to $0000 if the Interrupt enable register ($00) IET2 (bit1) is set to 1.
After the Timer2 control register ($27) T2GO (bit3) has been set to 1, writing the Timer2 load register ($384 - $387) can not
affect the up-counter operating anymore. Only when the Timer2 control register ($27) T2GO (bit3) has been cleared to 0, the
contents of the Timer2 load register ($384 - $387) will be loaded into the up-counter while the highest nibble ($387) is written.
The external clock source must follow certain constraints. The system clock samples it in instruction frame cycle. Therefore it
is necessary to be high at least 2 t
OSC
and low at least 2 t
OSC
. In this mode, the pre-scaler circuit will not affect the external
clock input. That means the input clock will bypass the pre-scaler circuit and disregards the value in Timer2 pre-scaler
register. So, the limitation is applied to the external clock period time (T
E
) described as follows:
T
E
(period time)
≥
4 * t
OSC
+ 2 *
∆
T
;
∆
T = 20ns
