Smart Machine Smart Decision
SIM5360_Hardware Design_V1.01
2013-11-22
62
Appendix
A. System Design
C103
C102
C101
VBAT_RF
VBAT_RF
Power supply
100uF
100nF
22pF
UART_TXD
UART_RXD
UART_CTS
UART_RTS
UART_RI
UART_DCD
UART_DTR
C109
220nF
V_USIM
USIM_RESET
USIM_CLK
USIM_DATA
62
63
Power supply
R101
61
64
GND
GND
GND
POWER_ON
RESET
3
4
Reset impulse
20~200ms
4.7K
47K
Turn on/off impulse
>50ms
UART_TXD
UART_RXD
UART_CTS
UART_RTS
UART_RI
UART_DCD
UART_DTR
71
68
67
66
69
70
72
23
1
GND
GND
0R
C107
C106
Main Antenna
NC
NC
MAIN_ANT
59
58
GND
GND
57
C107
G
NSS
Antenna
33pF
79
78
GND
GND
77
NC
L101
NC
L102
GND
80
GND
60
SIM_DATA
SIM_VDD
SIM_RST
SIM_CLK
SMF05C
SD
_
D3
SD
_
CLK
SD
_
D2
SD
_
D1
SD
_
CMD
SD
_
D0
24
26
25
22
21
GPIO4
USB_VBUS
RF ON/OFF
11
12
GPIO1
10K
10K
300R
LED
Network
Status
USB_DP
13
32
USB_DM
USB_VBUS
USB_DM
USB_DP
28
27
31
36
29
33
35
30
3
4
KEYSENSE_N0
KEYSENSE_N
2
KEYSENSE_N
1
KEYSENSE_N
3
KEYPAD_0
KEYSENSE_N
4
KEYPAD_
1
KEYPAD_
3
KEYPAD_
2
KEYPAD_
4
76
74
75
73
6
7
9
8
45
PCM_DIN/GPIO0
PCM_DOUT/GPIO5
PCM_SYNC/GPIO2
PCM_CLK/GPIO3
SPI_CLK
_N
SPI_MISO_DATA
SPI_CS
SPI_MOSI_DATA
CURRENT_SINK
1
2
3
4
5
6
7
8
9
*
0
#
Audio CODEC Chip
or
DSP
LCD
Display
52
54
VREG_
SD
VREG_
SD
44
IIC_SCL
I2C_SCL
55
IIC_S
DA
I2C_SDA
56
HKADC
HKADC
Input range:0-2.2V
TEMP_DET
47
46
R
eserve
R
eserve
15
16
VRTC
17
19
18
20
42
C108
If
RTC is
unused
,
keep
VRTC pin
open.
GPIO40
51
53
50
48
49
GPIO41
GPIO42
GPIO43
GPIO44
5
GND
GND
2
10
14
GND
GND
GND
GND
DC Output:
1.75
-3V
R102
R103
R104
R105
R106
R107
TVS
If
USB interface is
used
,
connect
USB_VBUS to DC
-5.25V
100uF
0R
C104
C105
Antenna
NC
NC
GND
Figure 44: System design