Si886xxISO-EVB
Rev. 0.1
3
2. Alternative Configurations
2.1. Disabling the DC-DC Converter
The SH_FC input (U1 pin 7) disables the dc-dc converter. JP9 controls the SH_FC input, enabling the converter
when pulled low, ON, and disabling the converter when pulled high, OFF. To disable the dc-dc converter, place the
jumper in the OFF position on JP9.
If interfacing to an external controller through the JP9 header, the controller must drive SH low for normal operation
and high to disable the dc-dc.
Note:
When the dc-dc converter is disabled, the B-side can be powered by an active high digital input on the B-side. Ensure B2
input is tri-state or driven low when VDDB is left floating or grounded.
2.2. 3.3 V DC-DC Converter Output
To change VOUT to 3.3 V, change R5 to 43.2 k
and R6 to 20.0 k
.
2.3. Alternate Supply for VDDA
To bypass the regulator circuit and supply VDDA from a separate supply, remove Q2 and connect positive power
supply through JP9 pin 3 and connect the supply return to J1 pin 2.
2.4. Alternate Supply for VDDB
To supply VDDB from a separate supply, remove the jumper on JP13 and supply desired power through JP13 pin 2
and connect the supply return to J2 pin 1.
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