Silicon Laboratories Si5328-EVB, Руководство пользователя

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Si5328-EVB
Rev. 0.1 3
5.2. Si5328 Input and Output Clocks
The Si5328 has two differential inputs that are ac terminated to 50

and then ac coupled to the part. Single-ended
operation can be implemented by simply not connecting to one of the two of the differential pairs bypassing the
unused input to ground with a capacitor. When operating with clock inputs of 1 MHz or less in frequency, the
appropriate dc blocking capacitors (C39, C41, C34, and C36) located on the bottom of the board should be
replaced with 0

resistors. It may also be necessary to remove the 50

ac termination to ground and use source
series termination located at the driver. If this approach is used, the onboard ac termination should be removed
(e.g. R46 or C40). The reason for this is that the capacitive reactance of the ac coupling capacitors becomes
significant at low frequencies. It is also important that the CKIN signal meet the minimum rise time of 11 ns (CKNtrf)
even though the input frequency is low.
Two jumpers are provided to assist in monitoring the Si5328 power: When R27 is removed, J20 can be used to
measure the device current. J20 can be used at any time to monitor the supply voltage at the device.
The Si5328 requires an external TCXO/OCXO reference so that it can operate as an ultra-narrowband jitter
attenuator with a loop bandwidth as low as 0.05. The range of acceptable reference frequencies is described in the
Any-Frequency Precision Clocks Family Reference Manual (Si53xxRM.pdf). The EVB is shipped with a Rakon
TCXO that was used for the G.8262 compliance tests.
The Si5328-EVB can be used with the on-board TCXO or an external reference oscillator. If the on-board TCXO
is in use, its Vdd can be either 3.3 V or the DUT Vdd, with the default connection being to Vdd.
If an external reference oscillator is in use, it can be either single-ended or differential. To use an external oscillator,
make the following changes:
1. Remove R64 so that the TCXO power is removed
2. Remove R62 to isolate the output of the TCXO
3. Install R61 to establish a connection to J2
4. Change R9 to a 50

resistor for proper termination
For single-ended operation, connect the reference signal to J2 and leave J1 open.
5.3. External Control and Status Headers
J17 is a ten pin ribbon header that is provided so that an external processor can control the Si5328 over either the
SPI or I
2
C bus. J17 can also be used to control an external Si5328 with the onboard MCU.
J14 is another ten pin ribbon header that brings out all of the status outputs from the Si5328. Note that some pins
are shared and serve as both inputs and outputs, depending on how the device is configured. For users who wish
to remotely access the input and output pin settings as well as serial ports with external hardware, both of these
headers can be connected to ribbon cables.
5.4. CPLD and Power
This CPLD is required for the MCU to control the Si5328. The CPLD provides two main functions: it translates the
voltage level from 3.3 V (the MCU voltage) to the Si5328 voltage (either 1.8, 2.5, or 3.3 V). The MCU
communicates to the CPLD with the SPI signals SS_CPLD_B (slave select), MISO (master in, slave out), MOSI
(master out, slave in), and SCLK. The MCU can talk to CPLD-resident registers that are connected to pins that
control the Si5328's pins, mainly for pin control mode. When the MCU wishes to access an Si5328 register, the SPI
signals are passed through the CPLD, while being level translated, to the Si5328. The CPLD is an EE device that
retains its code and is loaded through the JTAG port (J27). The core of the CPLD runs at 1.8 V, which is provided
by voltage regulator U6. The CPLD also logically connects many of the LEDs to the appropriate Si5328 pins.