S i 5 2 1 4 7 - E V B
4
Rev. 0.1
1.1. Generating DIFF Outputs from the Si52147
Upon power-on of the device, if the input pins are left floating, by default all DIFF outputs DIFF[0:8] are ON with
100 MHz and with spread spectrum disabled. The input pin headers have clear indication of jumper settings for
setting logic low (0) and high (1) as shown below, the jumper placed on middle and left pin will set input OE0 to
LOw; and jumper placed on middle and right pin will set input OE0 to high.
The output enable pins can be changed on the fly to observe outputs stopped cleanly. To enable the spread
spectrum, the SSON input needs to change from a logic level low to high. Input functionality is explained in detail
below.
1.1.1. SSON Input
Apply the appropriate logic level to SSON input to achieve clock frequency selection. When the SSON is high,
–0.5% down spread is enabled on all differential outputs with a saw-tooth spread profile. When the SSON is low,
spread profile is disabled.
1.1.2. OE [0:8] Input
The output enable pins can change on the fly when the device is on. Deasserting (valid low) results in
corresponding DIFF output to be stopped after their next transition with final state low/low. Asserting (valid high)
results in corresponding output that was stopped are to resume normal operation in a glitch-free manner.
Each of the hardware OE [0:8] pins are mapped via I
2
C to control bit in Control register. The hardware pin and the
Register Control Bit both need to be high to enable the output. Both of these form an “AND” function to disable or
enable the DIFF output. The DIFF outputs and their corresponding I
2
C control bits and hardware pins are listed in
Table 3.
Table 3. Output Enable Control
I
2
C Control Bit
Output
Hardware Control Input
Byte1 [bit 4]
DIFF0
OE0
Byte1 [bit 2]
DIFF1
OE1
Byte2 [bit 1]
DIFF2
OE2
Byte2 [bit 0]
DIFF3
OE3
Byte1 [bit 7]
DIFF4
OE4/5
Byte1 [bit 6]
DIFF5
OE4/5
Byte2 [bit 5]
DIFF6
OE6/8
Byte2 [bit 4]
DIFF7
OE6/8
Byte2 [bit 3]
DIFF8
OE6/8
Содержание Si52147
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