Silicon Laboratories Si3482 SMART PSE-24 KIT, Руководство пользователя, Страница: 8 / 22

S i 3 4 8 2 S m a r t P S E - 2 4 U G
8 Rev. 0.2
4.2. Schematics
The following figures show the detailed schematics, BOM, and layout for the Si3482evaluation board.
PWR Status LED
INPUT POWER
SILABS DEBUG HEADER
CONNECT
OR PIN DEF
INIT
ION
1
UART
_
R
X
3
UART
_
T
X
5 POE_DISABLE_PORT
Sn
7 I2C
_
SC
L
9 I2C
_
SD
A
11 POE_RESET
n
1
3
SW
_
P
OW
ER_
GOOD1
1
5
SW
_
P
OW
ER_
GOOD2
2 POE_INT
n
4
BRD_
T
Y
PE
6 +3V3 8 +3V3 10 G
N
D
12 G
N
D
14 G
N
D
16 G
N
D
CONT
ROL HEADER
UNISOLAT
E
D
BULK DECOUPLING
Connect
t
o
E
G
ND at
Mount
Holes
Baud sel
e
ct
SPI/UART SELECT
SPI Non Iso
PS3
VO
U
T
0
VO
U
T
1
VO
U
T
3
VO
U
T
4
VO
U
T
5
VO
U
T
6
VO
U
T
7
VO
U
T
8
VO
U
T
9
VO
U
T
1
0
VO
U
T
1
1
VO
U
T
1
2
VO
U
T
1
3
VO
U
T
1
6
VO
U
T
1
7
VO
U
T
1
8
VO
U
T
1
9
VO
U
T
2
0
VO
U
T
2
1
VO
U
T
2
2
VO
U
T
2
3
VIO
SC
L
1
R
ESETn
+1V
1
RE
G
+1V
1
RE
G
SD
A1
+1.
24RE
G
RX
_HOS
T
TX_H
OST
P
GOOD1
P
GOOD2
VO
U
T
2
VO
U
T
1
4
VO
U
T
1
5
R
ESETn
IN
T1
RX
TX
RE
S
E
Tn_HOS
T
R
ESETn
+3V3
-52V
+3V3
+3V3
+3V3
-52V
+3V
3
+3V
3
-52V
+3V
3
+3V
3
-52V
-52V
+3V
3
+3V3LV
+3V
3LV
+3V
3
+3V3LV
C819 0.
1uF
C819 0.
1uF
R839 10K R839 10K
R805 1K R805 1K
R838 10K R838 10K
TP
V
804
TPV TP
V
804
TPV
R832 10K R832 10K
C817 680pF C817 680pF
C802
0.
1uF
C802
0.
1uF
R804
1K
R804
1K
TP
V
802
TPV TP
V
802
TPV
J4
H
EAD
ER
1
2
x
2
J4
H
EAD
ER
1
2
x
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
R836 267 R836 267
U801 TLV
431
U801 TLV
431
R833
267
R833
267
SW
1
SW
PU
SH
BU
TTO
N
SW
1
SW
PU
SH
BU
TTO
N
+
C813 33uF
+
C813 33uF
C815 10uF C815 10uF
JP
5
H
EAD
ER
1
x
3
JP
5
H
EAD
ER
1
x
3
JP
7
HE
A
D
E
R
1x
3
JP
7
HE
A
D
E
R
1x
3
Is
olat
ion
RX
TX
RX_HO
S
T
TX
_HO
S
T
+3V3
GND
+3V3LV
EGND
RESET
n_HOST
RESET
n
PGOOD
1
_
IN
PGOOD
2
_
IN
PGOOD
1
_
OU
T
PGOOD
2
_
OU
T
R837 2.
1K
R837 2.
1K
TP
V
805
TPV TP
V
805
TPV
TP
V
807
TPV TP
V
807
TPV
JP
8
H
EAD
ER
1
x
3
JP
8
H
EAD
ER
1
x
3
R834 2.
1K
R834 2.
1K
TP
V
803
TPV TP
V
803
TPV
U802 S
i3482
U802 S
i3482
MISO
1
GND
3
VDD
4
RST
5
RSVD
6
RSVD
7
RSVD
8
MOSI
24
PSLCT
13
BAUD2
14
PS2
11
RSVD
9
PS3
10
PS1
12
SCL
17
NSS
23
BAUD1
15
BAUD0
16
SCK
2
SDA
18
INT
19
RSVD
20
RX
21
TX
22
GND
EPAD
-52V
NI
-52V
NI
TP
V
808
TPV TP
V
808
TPV
R802 10K R802 10K
R14 1K R14 1K
VR
EG
-52V
->+3.
3
V
Convert
e
r
+3V
3
+3V3_RTN
-48V -48V_RTN
J817 H
EAD
ER
5
x
2
J817 H
EAD
ER
5
x
2
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
C818 680pF C818 680pF
J5
HE
A
D
E
R
12x
2
J5
HE
A
D
E
R
12x
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
JP
6
H
EAD
ER
1
x
3
JP
6
H
EAD
ER
1
x
3
J809
5X
2 S
hrouded Header
P
S
U Debug
J809
5X
2 S
hrouded Header
P
S
U Debug
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
+
C814
33uF
+
C814
33uF
R840 10K R840 10K
J815 26-60-5080 J815 26-60-5080
1 2 3 4 5 6 7 8
R835 0 R835 0
R15 10K R15 10K
+3V3
NI
+3V3
NI
C816 0.
1uF
C816 0.
1uF
TP
803
GND TP
803
GND
LineFeeds
+3V3
+3V3_RTN
-52V
VREF
_IN
RESET
_L
VOUT
1
VOUT
2
VOUT
3
VOUT
4
VOUT
19
VOUT
20
VOUT
10
VOUT
21
VOUT
11
VOUT
22
VOUT
12
VOUT
5
VOUT
23
VOUT
6
VOUT
13
VOUT
7
VOUT
14
VOUT
8
VOUT
15
VOUT
9
VOUT
16
VOUT
17
VOUT
0
VOIT
18
SDA SCL INT
-52V_RTN
TP
V
806
TPV TP
V
806
TPV
D801
M
B
RS
3100T3
D801
M
B
RS
3100T3
+
C812 33uF
+
C812 33uF
R830
1K
R830
1K
D803 G
R
EEN
3.
3V
P
W
R
D803 G
R
EEN
3.
3V
P
W
R
JP
4
H
EAD
ER
1
x
3
JP
4
H
EAD
ER
1
x
3
R841 332 R841 332
TP
804
GND TP
804
GND
C810 0.
1uF
C810 0.
1uF
JP
9
H
EAD
ER
1
x
3
JP
9
H
EAD
ER
1
x
3
J816
H
EAD
ER
8
x
2
J816
H
EAD
ER
8
x
2
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
13
13
15
15
12
12
14
14
16
16
C803 4.
7uF
C803 4.
7uF
Figure
9.
S
i3
482 power man
ager and to
p level
board sch
ematic