
SPI Slave Timing
Table 4.42. SPI Slave Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK period
t
SCLK
6 *
t
HFPERCLK
—
—
ns
t
SCLK_HI
2.5 *
t
HFPERCLK
—
—
ns
SCLK low time
t
SCLK_LO
2.5 *
t
HFPERCLK
—
—
ns
t
CS_ACT_MI
4
—
70
ns
CS disable to MISO
t
CS_DIS_MI
4
—
50
ns
MOSI setup time
t
SU_MO
12.5
—
—
ns
t
H_MO
13
—
—
ns
SCLK to MISO
t
SCLK_MI
6 + 1.5 *
t
HFPERCLK
—
45 + 2.5 *
t
HFPERCLK
ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of V
DD
(figure shows 50% of V
DD
).
3. t
HFPERCLK
is one period of the selected HFPERCLK.
CS
SCLK
CLKPOL = 0
MOSI
MISO
t
CS_ACT_MI
t
SCLK_HI
t
SCLK
t
SU_MO
t
H_MO
t
SCLK_MI
t
CS_DIS_MI
t
SCLK_LO
SCLK
CLKPOL = 1
Figure 4.2. SPI Slave Timing Diagram
MGM13S Mighty Gecko SiP Module Data Sheet
Electrical Specifications
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