2. Guidelines for Layout Design When Using EFR32 Wireless MCUs
Some general guidelines for designing RF-related layouts for good RF performance are:
• For custom designs, use the same number of PCB layers as are present in the reference design whenever possible. Deviation from
the reference PCB layer count can cause different PCB parasitic capacitances, which can detune the matching network from its opti-
mal form. If a design with a different number of layers than the reference design is necessary, make sure that the distance between
the top layer and the first inner layer is similar to that found in the reference design, because this distance determines the parasitic
capacitance value to ground. Otherwise, detuning of the matching network is possible, and fine tuning of the component values may
be required.
• Use as much continuous and unified ground plane metallization as possible, especially on the top and bottom layers.
• Avoid the separation of the ground plane metallization, especially between the ground of the matching network and the RFIC GND
pins / exposed pad.
• Use as many grounding vias (especially near the GND pins) as possible to minimize series parasitic inductance between the ground
pours of different layers and between the GND pins.
• Use a series of GND stitching vias along the PCB edges and internal GND metal pouring edges. The maximum distance between
the vias should be less than lambda/10 of the 10
th
harmonic (the typical distance between vias on reference radio boards is 40–50
mil). This distance is required to reduce the PCB radiation at higher harmonics caused by the fringing field of these edges.
• For designs with more than two layers, it is recommended to put as many traces (even the digital traces) as possible in an inner
layer and ensure large, continuous GND pours on the top and bottom layers.
• Avoid using long and/or thin transmission lines to connect the RF related components. Otherwise, due to their distributed parasitic
inductance, some detuning effects can occur. Also shorten the interconnection lines as much as possible to reduce the parallel para-
sitic caps to the ground. However, couplings between neighbor discretes may increase in this way.
• To reduce the coupling between the nearby discrete inductors, avoid placing them in the same orientation.
• Use tapered line between transmission lines with different width (i.e., different impedance) to reduce internal reflections.
• Avoid using loops and long wires to obviate their resonances. They also work well as unwanted radiators, especially at the harmon-
ics.
• Always ensure good V
DD
filtering by using some bypass capacitors (especially at the range of the operating frequency). The series
self-resonance of the capacitor should be close to the filtered frequency. The bypass capacitor which filters the highest frequency
should be placed closest to the V
DD
pins of the EFR32. In addition to the fundamental frequency, the crystal/clock frequency and its
harmonics (up to the 3
rd
) should be filtered to avoid up-converted spurs.
• Connect the crystal case to the ground using many vias to avoid radiation of the ungrounded parts. Do not leave any metal uncon-
nected and floating that may be an unwanted radiator. Avoid leading supply traces close or beneath the crystal or parallel with a
crystal signal or clock trace.
• Place the RF related parts (especially the antenna) far away from the DC-DC converter output and the related DC-DC components.
• Avoid routing GPIO lines close or beneath the RF lines, antenna or crystal, or in parallel with a crystal signal. Use the lowest slew
rate possible on GPIO lines to decrease crosstalk to RF or crystal signals.
• Use as short V
DD
traces as possible. The V
DD
trace can be a hidden, unwanted radiator so it is important to simplify the V
DD
routing
as much as possible and use large, continuous GND pours with many stitching vias. To achieve the simplified V
DD
routing, try to
avoid star topology of V
DD
traces (i.e., avoid connecting all V
DD
traces in one common point).
• Using silkscreen near the antenna could slightly affect the dielectric environment of the antenna. Although this effect is usually negli-
gible, if possible, try to avoid using silkscreen on the antenna or on the antenna copper pour keep out areas.
AN928.1: EFR32 Series 1 Layout Design Guide
Guidelines for Layout Design When Using EFR32 Wireless MCUs
silabs.com
| Building a more connected world.
Rev. 0.5 | 5
