Silicon Laboratories CP2130, Руководство пользователя

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C P 2 1 3 0 - E K
24 Rev. 0.2
10.7. LED Headers (JP3, JP4, and JP5)
Headers JP3, JP4, and JP5 are provided to allow access to the GPIO pins on the CP2130. Place shorting blocks
on JP3, JP4, and JP5 to connect the GPIO pins to the ten green LEDs, D1–D10, and the one red LED, D11. These
LEDs can be used to indicate active communications through the CP2130. Table 5 lists the LED corresponding to
each header position.
10.8. SPI Loopback Header (JP6)
To short the SPI MOSI and MISO signals, install a shorting block on JP6. This shorting block should be removed
during normal SPI operation. See Table 6 for the SPI loopback header pin definitions.
10.9. ADC VDD Header (JP9)
This header provides access to the ADC VDD pin. Install a shorting block on JP9 to provide power to the ADC from
VIO. See Table 7 for the ADC VDD header pin definitions.
Table 5. JP3, JP4, and JP5 LED Header Locations
GPIO Pin LED Pins
GPIO.0 / CS0 D1 JP3[1:2]
GPIO.1 / CS1 D2 JP3[3:4]
GPIO.2 / CS2 D3 JP3[5:6]
GPIO.3 / CS3 / RTR D4 JP3[7:8]
GPIO.4 / CS4 / EVTCNTR D5 JP3[9:10]
GPIO.5 / CS5 / CLKOUT D6 JP3[11:12]
GPIO.6 / CS6 D7 JP3[13:14]
GPIO.7 / CS7 D8 JP3[15:16]
GPIO.8 / CS8 / SPIACT D9 JP3[17:18]
GPIO.9 / CS9 / SUSPEND D10 JP4[1:2]
GPIO.10 / CS10 / SUSPEND D11 JP5[1:2]
Table 6. SPI Loopback Header Pin Definitions
Pin # Definitions
1 MISO
2 MOSI
Table 7. ADC VDD Header Pin Definitions
Pin # Definitions
1 VIO
2 ADC VDD