Offset
Name
Description
0x100
pmuwakeupi0
Wakeup program instruction 0
0x104
pmuwakeupi1
Wakeup program instruction 1
0x108
pmuwakeupi2
Wakeup program instruction 2
0x10C
pmuwakeupi3
Wakeup program instruction 3
0x110
pmuwakeupi4
Wakeup program instruction 4
0x114
pmuwakeupi5
Wakeup program instruction 5
0x118
pmuwakeupi6
Wakeup program instruction 6
0x11C
pmuwakeupi7
Wakeup program instruction 7
0x120
pmusleepi0
Sleep program instruction 0
0x124
pmusleepi1
Sleep program instruction 1
0x128
pmusleepi2
Sleep program instruction 2
0x12C
pmusleepi3
Sleep program instruction 3
0x130
pmusleepi4
Sleep program instruction 4
0x134
pmusleepi5
Sleep program instruction 5
0x138
pmusleepi6
Sleep program instruction 6
0x13C
pmusleepi7
Sleep program instruction 7
0x140
pmuie
PMU Interrupt Enables
0x144
pmucause
PMU Wakeup Cause
0x148
pmusleep
Initiate PMU Sleep Sequence
0x14C
pmukey
PMU Key. Reads as 1 when PMU is unlocked
The
pmukey
register has one bit of state. To prevent spurious sleep or PMU program modifica-
tion, all writes to PMU registers must be preceded by an unlock operation to the
pmukey
register
location, which sets
pmukey
to 1. The value
0x51F15E
must be written to the
pmukey
register
address to set the state bit before any write access to any other PMU register. The state bit is
reset at AON reset, and after any write to a PMU register.
Table 38:
PMU Memory Map
Chapter 14 Power-Management Unit (PMU)
FE310-G003 Manual
© SiFive, Inc.
Page 68
Содержание FE310-G003
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