Universal Asynchronous Receiver/
Transmitter (UART)
This chapter describes the operation of the SiFive Universal Asynchronous Receiver/Transmit-
ter (UART).
The UART peripheral supports the following features:
• 8-N-1 and 8-N-2 formats: 8 data bits, no parity bit, 1 start bit, 1 or 2 stop bits
• 8-entry transmit and receive FIFO buffers with programmable watermark interrupts
• 16× Rx oversampling with 2/3 majority voting per bit
The UART peripheral does not support hardware flow control or other modem control signals, or
synchronous serial data transfers.
FE310-G002 contains two UART instances. Their addresses and parameters are shown in
Table 54.
Instance Num-
ber
Address
div_width
div_init
TX FIFO
Depth
RX FIFO
Depth
0
0x10013000
16
3
8
8
1
0x10023000
16
3
8
8
Table 54:
UART Instances
79
Содержание FE310-G002
Страница 1: ...SiFive FE310 G002 Manual v19p05 SiFive Inc ...
Страница 11: ...Figure 1 FE310 G002 top level block diagram Copyright 2019 SiFive Inc All rights reserved 9 ...
Страница 15: ...Chapter 2 List of Abbreviations and Terms 13 ...
Страница 23: ...Chapter 4 Memory Map The memory map of the FE310 G002 is shown in Table 4 21 ...