Feature
Description
Available in
QFN48
RISC-V Core
1× E31 RISC‑V cores with machine and user mode,
16 KiB 2-way L1 I-cache, and 16 KiB data tightly inte-
grated memory (DTIM).
✔
Interrupts
Software and timer interrupts, 52 peripheral interrupts con-
nected to the PLIC with 7 levels of priority.
✔
UART 0
Universal Asynchronous/Synchronous Transmitters for
serial communication.
✔
UART 1
Universal Asynchronous/Synchronous Transmitters for
serial communication.
✔
QSPI 0
Serial Peripheral Interface. QSPI 0 has 1 chip select sig-
nal.
✔
(4 DQ lines)
SPI 1
Serial Peripheral Interface. SPI 1 has 4 chip select signals.
✔
(3 CS lines)
(2 DQ lines)
SPI 2
Serial Peripheral Interface. SPI 2 has 1 chip select signal.
PWM 0
8-bit Pulse-width modulator with 4 comparators.
✔
PWM 1
16-bit Pulse-width modulator with 4 comparators.
✔
PWM 2
16-bit Pulse-width modulator with 4 comparators.
✔
I²C 0
Inter-Integrated Circuit (I²C) controller.
✔
GPIO
32 General Purpose I/O pins.
✔
Always On
Domain
Supports low-power operation and wakeup.
✔
Table 1:
FE310-G002 Feature Summary.
The FE310-G002 includes a 32-bit E31 RISC‑V core, which has a high-performance single-
issue in-order execution pipeline, with a peak sustainable execution rate of one instruction per
clock cycle. The E31 core supports Machine and User privilege modes as well as standard Mul-
tiply, Atomic, and Compressed RISC‑V extensions (RV32IMAC).
The core is described in more detail in Chapter 3.
The FE310-G002 includes a RISC-V standard platform-level interrupt controller (PLIC), which
supports 52 global interrupts with 7 priority levels. The FE310-G002 also provides the standard
RISC‑V machine-mode timer and software interrupts via the Core-Local Interruptor (CLINT).
Interrupts are described in Chapter 8. The CLINT is described in Chapter 9. The PLIC is
described in Chapter 10.
Copyright © 2019, SiFive Inc. All rights reserved.
10
Содержание FE310-G002
Страница 1: ...SiFive FE310 G002 Manual v19p05 SiFive Inc ...
Страница 11: ...Figure 1 FE310 G002 top level block diagram Copyright 2019 SiFive Inc All rights reserved 9 ...
Страница 15: ...Chapter 2 List of Abbreviations and Terms 13 ...
Страница 23: ...Chapter 4 Memory Map The memory map of the FE310 G002 is shown in Table 4 21 ...