Interrupt Control Status Registers
The E31 Core Complex specific implementation of interrupt CSRs is described below. For a
complete description of RISC‑V interrupt behavior and how to access CSRs, please consult
The
RISC‑V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10
.
The
mstatus
register keeps track of and controls the hart’s current operating state, including
whether or not interrupts are enabled. A summary of the
mstatus
fields related to interrupts in
the E31 Core Complex is provided in Table 5. Note that this is not a complete description of
mstatus
as it contains fields unrelated to interrupts. For the full description of
mstatus
, please
consult the
The RISC‑V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10
.
Machine Status Register
CSR
mstatus
Bits
Field Name
Attr.
Description
[2:0]
Reserved
WPRI
3
MIE
RW
Machine Interrupt Enable
[6:4]
Reserved
WPRI
7
MPIE
RW
Machine Previous Interrupt Enable
[10:8]
Reserved
WPRI
[12:11]
MPP
RW
Machine Previous Privilege Mode
Table 5:
E31 Core Complex
mstatus
Register (partial)
Interrupts are enabled by setting the MIE bit in
mstatus
and by enabling the desired individual
interrupt in the
mie
register, described in Section 5.3.2.
Machine Interrupt Enable Register (
Individual interrupts are enabled by setting the appropriate bit in the
mie
register. The
mie
regis-
ter is described in Table 6.
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