Chapter 14
One-Time Programmable Memory
(OTP) Peripheral
This chapter describes the operation of the One-Time Programmable Memory (OTP) Controller
on SiFive systems.
Device configuration and power-supply control is principally under software control. The controller
is reset to a state that allows memory-mapped reads, under the assumption that the controller’s
clock rate is between 1 MHz and 37 MHz.
vrren
is asserted during synchronous reset; it is safe to
read from OTP immediately after reset if reset is asserted for at least ???
µ
s while the controller’s
clock is running.
Programmed-I/O reads and writes are sequenced entirely by software.
Memory Map
The memory map for the OTP control registers is shown in Table 14.1. The control-register mem-
ory map has been designed to only require naturally aligned 32-bit memory accesses. The OTP
controller also contains a read sequencer, which exposes the OTP’s contents as a read/execute-
only memory-mapped device.
Programmed-I/O lock register (
otp lock
)
The
otp lock
register supports synchronization between the read sequencer and the
programmed-I/O interface. When the lock is clear, memory-mapped reads may proceed. When
the lock is set, memory-mapped reads do not access the OTP device, and instead return
0
imme-
diately.
The
otp lock
should be acquired before writing to any other control register. Software can attempt
to acquire the lock by storing
1
to
otp lock
. If a memory-mapped read is in progress, the lock will
not be acquired, and will retain the value
0
. Software can check if the lock was successfully
acquired by loading
otp lock
and checking that it has the value
1
.
After a programmed-I/O sequence, software should restore the previous value of any control reg-
isters that were modified, then store
0
to
otp lock
.
Figure 14.1 shows the synchronization code sequence.
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