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AC75 Hardware Interface Description
Strictly confidential / Preliminary
s
AC75_HD_V00.202
Page 71 of 120
27.04.2006
The timing of a PCM
short frame
is shown in Figure 29. 16-bit data are transferred in both
directions at the same time during the first 16 clock cycles after the frame sync pulse. The
duration of a frame sync pulse is one BITCLK period, starting at the rising edge of BITCLK.
TXDAI data is shifted out at the next rising edge of BITCLK. Data transmitted from RXDAI of
the internal application is sampled at the falling edge of BITCLK.
BITCLK
TXDAI
RXDAI
FS
MSB
MSB
LSB
LSB
14
13
14
13
1
1
12
12
2
2
MSB
MSB
125 µs
Figure 29: Short Frame PCM timing
The timing of a PCM
long frame
is shown in Figure 30. 16-bit data are transferred in both
directions at the same time during the frame sync pulse FS is high. For this reason the
duration of a frame sync pulse is 16 BITCLK periods, starting at the rising edge of BITCLK.
TXDAI data is shifted out at the same rising edge of BITCLK. Data transmitted from RXDAI of
the internal application is sampled at the falling edge of BITCLK.
BITCLK
TXDAI
RXDAI
FS
MSB
MSB
LSB
LSB
14
13
14
13
1
1
12
12
2
2
MSB
MSB
125 µs
Figure 30: Long Frame PCM timing