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AGP Fast Write
This item enables an end user to manually select the AGP output buffer
drive strength.
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The Choice: Enabled or Disabled.
AGP Master 1 WS Write
When this item enabled, writing to the AGP(Accelerated Graphics Port)
is executed with one wait state.
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The Choice: Enabled or Disabled.
AGP Master 1 WS Read
When this item enabled, reading from the AGP (Accelerated Graphics
Port) is executed with one wait state.
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The Choice: Enabled or Disabled.
CPU & PCI Bus Control
Options are in its sub-menu.
Press <Enter> to enter the sub-menu of detailed options.
CPU to PCI Write Buffer
When this field is Enabled, the writing from CPU to PCI bus is buffered,
to compensate for the speed differences between the CPU and the PCI
bus. When Disabled, the writing is are not buffered and the CPU must
wait until the write is complete before starting another write cycle.
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The Choice: Enabled or Disabled.
PCI Master 0 WS Write
When this item enabled, writing to the PCI bus is executed with zero
wait state.
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The Choice: Enabled or Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with
PCI specification version 2.1.
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The Choice: Enabled or Disabled.
Memory Hole
In order to improve performance, some space in memory can be
reserved for ISA cards.
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The Choice: Disabled or 15M-16M.
