User's Manual 21
MA Additional Wait State
When enabled, one additional wait state is inserted before the assertion of the first memory
address line MA and CAS/RAS assertion during DRAM read or write leadoff cycles.
RAS To CAS# Delay
When DRAM is refreshed, both rows and columns are address separately. This setup item
allows you to determine the timing of the transition from Row Address Strobe (RAS) to
Column Address Strobe (CAS). The options are
enabled
for 3 and
disabled
for 2
CLKs.
DRAM Read Burst (B/E/F)
This item set the BEDO/EDO/FPM DRAM Read Burst Timing. The timing used
depends on the type of DRAM (EDO burst mode or standard fast page mode) on a per-
bank basis. The options are
x1/2/3, x2/2/3
,
x2/3/4
and
x3/4/4
.
DRAM Write Burst (B/E/F)
This item set the BEDO/EDO/FPM DRAM Write Burst timing for accessing DRAM.
The options are
x2/2/3, x3/3/3, x3/3/4, x4/4/4
.
ISA Clock
This item allows the user to set ISA clock that divide from PCI clock by 3 or by 4. For
example, if 200MHz Pentium Pro processor is used, PCI clock will be 33MHz, ISA Clock
will be 8.25MHz when PCI clock divided by 4, and 11MHz when PCI clock divided by 3.
DRAM Refresh Queue
When enabled, the chipset's internal 4-deep refresh queue is enabled with 4th request
being the priority request. All refresh requests are queued. If disabled, the refresh queue
is disabled and all refreshes are priority requests.
DRAM RAS Only Refresh
This item allows the user to the RAS only refresh or CAS before RAS refresh.
DRAM ECC/PARITY Select
When using parity DRAM modules, you can select from the options of ECC (Error
Checking and Correcting) or Parity to correct 1 bit memory errors that may occur in the
memory. When using no parity DRAM modules, this function is not available.
Fast DRAM Refresh
When disabled will execute the normal mode where the refresh rate is every 15ns, when
enabled, the fast refresh mode implements a refresh cycle every 32 host cycle.
Read-Around-Write
When enabled will increase the execution efficiency of the processor. It allows the
processor to execute read commands out of order if there is independence between these
read and other write commands.
