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AGP Driving Control
This item has the system automatically select its output buffer drive
strength, or makes it manually selectable by an end-user.
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The Choice: Auto or Manual.
AGP Driving Value
This item defines the AGP output buffer drive strength.
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Key in a HEX number: Min=0000, Max=00FF.
AGP Fast Write
This item enables or disables the fast written function for the AGP card.
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The Choice: Disabled or Enabled.
AGP Master 1 WS Write
When Enabled, writing to the AGP is implemented with a single delay.
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The Choice: Disabled or Enabled.
AGP Master 1 WS Read
When Enabled, reading to the AGP is implemented with a single delay.
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The Choice: Disabled or Enabled.
DBI Output for AGP Trans.
This item is used to improve the signal quality for the AGP 3.0.
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The Choice: Disabled or Enabled.
CPU & PCI Bus Control
Press <Enter> to enter into the detailed options.
CPU to PCI Write Buffer
When Enabled, writing from the CPU to PCI bus is buffered, to compen-
sate for the speed differences between them. When Disabled, the
writing is not buffered and the CPU must wait until the writing is com-
plete before starting another writing cycle.
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The Choice: Enabled or Disabled.
PCI Master 0 WS Write
When Enabled, writing to the PCI bus is implemented with no delay.
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The Choice: Enabled or Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit post written buffer to support
delay transactions cycles. Select Enabled to support compliance with
PCI specification version 2.1.
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The Choice: Enabled or Disabled.
