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PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with
PCI specification version 2.1.
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The choice: Enabled, Disabled.
PCI #2 Access #1 Retry
This item allows you enable/disable the PCI #2 Access #1 Retry.
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The choice: Enabled, Disabled.
AGP Master 1 WS Write
This implements a single delay when writing to the AGP Bus. By de-
fault, two-wait states are used by the system, allowing for greater
stability.
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The choice: Enabled, Disabled.
AGP Master 1 WS Read
This implements a single delay when reading to the AGP Bus. By
default, two-wait states are used by the system, allowing for greater
stability.
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The choice: Enabled, Disabled.
Memory Parity/ECC Check
This item allows you to Enabled/Disabled memory error checking and
correction (ECC). In order for ECC to function, 9-chip (8 memory chips
+ 1 ECC chip) SDRAM modules must be installed on the mainboard.
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The choice: Enabled, Disabled.
CPU Voltage Regulator
This item allows user to adjust CPU Vcore as below :
The user may fine tune CPU voltage. The voltage ranges vary with
processor installed which are PPGA & FC-PGA Celeron and Pentium III
processors.
We strongly recommend the user remain on "default" setting unless
you are familiar with CPU Vcore voltage.
Note:
Improper Vcore voltage may damage your processor.