Sharp SD-AT1000, Руководство по обслуживанию

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SD-AT1000
Figure 45 BLOCK DIAGRAM OF IC
IC101 VHiCS493264-1: DSP (CS493264) (3/3)
Pin No. Function
Terminal Name Input/Output
43 SCLK Input Bidirectional digital-audio output bit clock. SCLK can be an output that is derived
from MCLK to provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs, depending on the
MCLK rate and the digital-output configuration. SCLK can also be an input and
must be at least 48 Fs or greater. As an input, SCLK is independent of MCLK.
44 MCLK Input Bidirectional master audio clock. MCLK can be an output from the CS493XX that
provides an oversampled audio-output clock at either 128 Fs, 256 Fs, or 512 Fs.
MCLK can be an input at 128 Fs, 256 Fs, 384 Fs, or 512 Fs. MCLK is used to
derive SCLK and LRCLK when SCLK and LRCLK are driven by the CS493XX.
1 2 3 4 5 6 40 41 42 43 44
23 22 21 20 19 18 28 27 26 25 24
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
IC101
CS493264
MCLK DGND1
CS
SCDIO, SCDOUT, PSEL, GPIO9
ABOOT, INTERQ EXTMEM, GPIO8
SDATAN1
VD3
DGND3
SCLKN1, STCCLK2
LRCLKN1
CMPDAT, SDATAN2
CMPCLK, SCLKN2
AUDATA3, XMT958 WR, DS, EMWR, GPIO10 RD, R/W, EMOE, GPIO11 A1, SCDIN AUDATA11 AUDATA1 AUDATA0 LRCLK SCLK
A0, SCCLK
VD2
DGND2
DATA7, EMDA7, GPIO7
DATA6, EMDA6, GPIO6
DATA5, EMDA5, GPIO5
DATA4, EMDA4, GPIO4
DATA3, EMDA3, GPIO3
DATA2, EMDA2, GPIO2
DATA1, EMDA1, GPIO1
DATA0, EMDA0, GPIO0
CMPREQ, LRCLKN2
CLKIN
CLKSEL
FILT2
FILT1
VA
AGND
RESET
DD
DC
AUDATA2