CG RAM Address Set
The address counter is loaded with a character
generator RAM address, expressed as a 6-digit
binary number. Following the execution of this in-
struction, subsequent data transactions will be be-
tween the external microprocessor and the
character generator RAM.
DD RAM Address Set
The address counter is loaded with a display data
RAM address, expressed as a 7-digit binary num-
ber. Following the execution of this instruction, sub-
sequent data transactions will be between the
external microprocessor and the display data RAM.
For N = 0 (single line display), the binary number,
A
DD
may have a value ranging from 00
H
to 4F
H
. For
N = 1 (dual line display), the binary number, A
DD
,
may have a value ranging from 00
H
to 27
H
for the
first line, or 40
H
to 67
H
for the second line.
Busy Flag/Address Counter Read
The busy flag (BF) is read out, and indicates
whether or not the LCD unit is still executing the
previous instruction. BF = 1 indicates the busy state
(internal operation), and the next instruction will not
be accepted until BF = 0. This instruction also reads
out the contents of the address counter, expressed
as a 7-digit binary number. The address counter is
used for accessing both the character generator
RAM and the display data RAM. On read-out, the
address counter will contain either a character gen-
erator RAM address or a display data RAM address,
as determined by the most recently executed ad-
dress set instruction.
CG RAM/DD RAM Data Write
An 8-bit data word is written into either the char-
acter generator RAM or display data RAM, as de-
termined by the most recently executed address set
instruciton. The data is written into the RAM location
specified by the address counter. After the data is
written into the RAM, the address counter is either
incremented or decremented by one, as determined
by the current entry mode. A display shift may also
take place after the data is written.
CG RAM/DD RAM Data Read
An 8-bit data word is read from either the charac-
ter generator RAM or display data RAM, as deter-
mined by a previously executed address set
instruction. The data is read from the RAM location
specified by the address counter.
This instruction must be immediately preceded by
the CG RAM address set instruction, the DD RAM
address set instruction, the cursor shift instruction,
or a previous CG RAM/DD RAM data read instruc-
tion. Any other preceding instruction will cause in-
valid data to be read. The address set instructions
cause the address counter to be loaded with a valid
data read address.
The cursor shift command allows selected DD
RAM data to be read without the necessity of reset-
ting the DD RAM address. Following the cursor shift
instruction, the CG RAM/DD RAM data read instruc-
tion will read data from the DD RAM.
After the execution of each data read instruction,
the address counter is either incremented or decre-
mented by one, as determined by the current entry
mode. It is not necessary to reset the RAM address
before the execution of subsequent data read in-
structions if the same RAM is to be read. The
display is not shifted by the data read instruction.
NOTE
After the execution of the CG RAM/DD RAM data write
instruction, the address counter is incremented or decre-
mented automatically. However, the contents of the RAM
location specified by the address counter cannot be read
by a subsequent CG RAM/DD RAM data read instruction.
The correct procedure for reading data from the CG RAM
or DD RAM is to execute an address set or cursor shift
instruction. Once a data read instruction has been exe-
cuted, successive data read instructions may be exe-
cuted, with no requirement for intervening instructions.
DB
0
DB
7
RS R/W
0
CODE
0
0
1
A
A
A
A
A
A
DB
0
DB
7
RS R/W
0
CODE
0
1
A
A
A
A
A
A
A
DB
0
DB
7
RS R/W
0
CODE
1
BF
A
A
A
A
A
A
A1
DB
0
DB
7
RS R/W
1
CODE
0
D
D
D
D
D
D
D
D
DB
0
DB
7
RS R/W
1
CODE
1
D
D
D
D
D
D
D
D
Dot-Matrix LCD Units
Display Unit User’s Manual
17
