Sharp LC-40LS340E, Руководство по обслуживанию

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LC-32LE340/343
LC-40LE340/343
28
The EM68B16C is a high-speed CMOS Double-Data-Rate-Two (DDR2), synchronous
dynamic random-access memory (SDRAM) containing 512 Mbits in a 16-bit wide data I/Os.
It is internally configured as a quad bank DRAM, 4 banks x 8Mb addresses x 16 I/Os The
device is designed to comply with DDR2 DRAM key features such as posted CAS# with
additive latency, Write latency = Read latency -1, Off-Chip Driver (OCD) impedance
adjustment, and On Die Termination(ODT). All of the control and address inputs are
synchronized with a pair of externally supplied differential clocks. Inputs are latched at the
cross point of differential clocks (CK rising and CK# falling) All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion. The address
bus is used to convey row, column, and bank address information in RAS #, CAS#
multiplexing style. Accesses begin with the registration of a Bank Activate command, and
then it is followed by a Read or Write command. Read and write accesses to the DDR2
SDRAM are 4 or 8-bit burst oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. Operating the four memory
banks in an interleaved fashion allows random access operation to occur at a higher rate than
is possible with standard DRAMs. An auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of the burst sequence. A sequential and
gapless data rate is possible depending on burst length, CAS# latency, and speed grade of the
device.
b) Pinning
28
The EM68B16C is a high-speed CMOS Double-Data-Rate-Two (DDR2), synchronous
dynamic random-access memory (SDRAM) containing 512 Mbits in a 16-bit wide data I/Os.
It is internally configured as a quad bank DRAM, 4 banks x 8Mb addresses x 16 I/Os The
device is designed to comply with DDR2 DRAM key features such as posted CAS# with
additive latency, Write latency = Read latency -1, Off-Chip Driver (OCD) impedance
adjustment, and On Die Termination(ODT). All of the control and address inputs are
synchronized with a pair of externally supplied differential clocks. Inputs are latched at the
cross point of differential clocks (CK rising and CK# falling) All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion. The address
bus is used to convey row, column, and bank address information in RAS #, CAS#
multiplexing style. Accesses begin with the registration of a Bank Activate command, and
then it is followed by a Read or Write command. Read and write accesses to the DDR2
SDRAM are 4 or 8-bit burst oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. Operating the four memory
banks in an interleaved fashion allows random access operation to occur at a higher rate than
is possible with standard DRAMs. An auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of the burst sequence. A sequential and
gapless data rate is possible depending on burst length, CAS# latency, and speed grade of the
device.
b) Pinning
44
LC-40LS340