Sharp LC-30HV2E, Руководство по обслуживанию

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51
LC-30HV2E
Ë
VH+-1Q (IC2201)
» TMDS Receiver
»
Block Diagram
PanelLink
48
LVDS
(1 channel)
DVI
DPMS
Microcontroller
24
PixelPrecision
Scaling
Dithering
Gamma Tuning
(2 LUTs )
Auto-Detect
Block
DVI-D
TMDS
Rx Core
Content
Protection
CP I
2
C
Interface
Configuration
I
2
C Interface
Power
Manageme nt
Control
Block
On Screen
Display Control
OSD Memory
(RAM)
Character
Generator
PWM 0
PWM 1
5X
Crystal
EDID PROM
Key PROM
DDC
Configuration
PROM
DVI-D
SiI 151
»
Pin Function
Pin Name Pin No. Type Description
QE[23-0] 86-79, Out Output Even Data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock in mode and to the first
24-bit pixel data for 2-pixels/clock mode. Output dat synchronized with output data clock (ODCK).
See section 21 on page 38 for the output data mapping of these pins.
QO[23:0] 158, Out Output Odd Data[23:0] corresponds to the second 24-bit pixel data for 2-pixels/clock mode. Dur-
ing 1-pixel/clock mode, these outputs are forced LOW.
Output data is synchronized with output data clock (ODCK). See section 21 on page 38 for the
output data mapping of these pins.
ODCK 93 Out Output Data Clock.
ODCK_D 102 Out Output Data Clock Delayed. Controlled by register VSD1[3:2] on page 82.
DE 95 Out Output Data Enable. This signal qualifies the active data area. A HIGH level signifies valid display
time. A LOW level signifies a valid blanking time.
HSYNC 97 Out Horizontal Sync control signal.
VSYNC 96 Out Vertical Sync control signal.
CTL1 / IVS 89 Out Control signals from the transmitter and internal XCLK or input HSYNC, input VSYNC, input DE
and input CLOCK (ICLK). RMDT[7] determines the function of these pins. See section 15 for
RMDT[7] control information. CTL 3 is also used as a strapping option to enable/disable the 5x
clock multiplier, high=bypass and low=enable 5x.
TX_0- 182 Analog LVDS output data pairs.
TX_0+ 181
TX_1- 180
TX_1+ 179
TX_2- 176
TX_2+ 175
TX_3- 172
TX_3+ 171
TX_CK- 174 Analog LVDS output clock pair.
TX_CK+ 173
SCL 165 I/O I 2 C Clock. This pin is open drain.
SDA 166 I/O I
2
C Data. This pin is open drain.
MSTATE 164 Out I 2 C Bus Master. The pin goes HIGH upon RESET LOW and goes LOW after the SiI861 has
finished mastering the I
2
C bus.
KEY_SCL 150 I/O Cipher Key I 2 C Clock. This pin is open drain.
KEY_SDA 149 I/O Cipher Key I 2 C Data. This pin is open drain.
DDC_SCL 152 I/O DDC/Authentication I
2
C Clock. This pin is open drain.
DDC_SDA 151 I/O DDC/Authentication I 2 C Data. This pin is open drain.
PD# 4 In Power Down (active LOW). A HIGH level (3.3V) indicates normal operation and a LOW level
indicates power down mode. Register FDIV[7] determines the power down mode entered: 1 =
Power down, 0 = Pull down
The I
2
C register values are retained in Power Down mode but the I
2
C interface is disabled.
ON_OFF / 7 Out On_Off / Loss of Sync. In non-DVI mode, a HIGH level indicates that the link from the transmitter
to the SiI861 is active. A LOW level indicates that the link from the transmitter to the SiI861 is not
active.
74-73,
33-28,
23-16
145-139,
132-125
122-117,
99-98
CTL2 / IHS 90 Out
CTL3 / IDE 91 Out
TPCLK 105 Out
L_SYNC#